constants as traits

rocket/src/main/scala/arbiter.scala

@@ -1,8 +1,7 @@
 package rocket
 
-import Chisel._;
+import Chisel._
-import Node._;
+import Node._
-import Constants._;
 import uncore._
 
 class ioUncachedRequestor extends Bundle {

rocket/src/main/scala/consts.scala

@@ -1,21 +1,40 @@
 package rocket
+package constants
 
 import Chisel._
 import scala.math._
 
-object Constants
+abstract trait MulticoreConstants {
-{
+  val NTILES: Int = 1
-  val NTILES = 1
+  val TILE_ID_BITS = log2Up(NTILES)+1
-  val HAVE_RVC = false
+}
-  val HAVE_FPU = true
-  val HAVE_VEC = true
 
-  val MAX_THREADS = 
+abstract trait CoherenceConfigConstants {
-      hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK
+  val ENABLE_SHARING: Boolean
+  val ENABLE_CLEAN_EXCLUSIVE: Boolean
+}
 
+trait UncoreConstants {
+  val NGLOBAL_XACTS = 8
+  val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS)
+}
+
+trait HTIFConstants {
   val HTIF_WIDTH = 16
   val MEM_BACKUP_WIDTH = HTIF_WIDTH
+}
 
+abstract trait TileConfigConstants extends UncoreConstants with MulticoreConstants {
+  val HAVE_RVC: Boolean
+  val HAVE_FPU: Boolean
+  val HAVE_VEC: Boolean
+  def FPU_N = UFix(0, 1)
+  def FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N
+  def VEC_N = UFix(0, 1);
+  def VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N
+}
+
+trait ScalarOpConstants {
   val BR_X    = Bits("b????", 4)
   val BR_N    = UFix(0, 4);
   val BR_EQ   = UFix(1, 4);
@@ -89,7 +108,9 @@ object Constants
   val DW_XPR = Y
 
   val RA = UFix(1, 5);
+}
 
+trait MemoryOpConstants {
   val MT_X  = Bits("b???", 3);
   val MT_B  = Bits("b000", 3);
   val MT_H  = Bits("b001", 3);
@@ -116,7 +137,9 @@ object Constants
   val M_XA_MAX  = Bits("b1101", 4);
   val M_XA_MINU = Bits("b1110", 4);
   val M_XA_MAXU = Bits("b1111", 4);
+}
 
+trait PCRConstants {
   val PCR_X = Bits("b???", 3)
   val PCR_N = Bits(0,3)
   val PCR_F = Bits(1,3) // mfpcr
@@ -161,11 +184,15 @@ object Constants
   val SR_VM   = 8   // VM enable
   val SR_IM   = 16  // interrupt mask
   val SR_IM_WIDTH = 8
+}
 
+trait InterruptConstants {
   val CAUSE_INTERRUPT = 32
   val IRQ_IPI = 5
   val IRQ_TIMER = 7
+}
  
+trait AddressConstants { 
   val PADDR_BITS = 40;
   val VADDR_BITS = 43;
   val PGIDX_BITS = 13;
@@ -173,8 +200,9 @@ object Constants
   val VPN_BITS = VADDR_BITS-PGIDX_BITS;
   val ASID_BITS = 7;
   val PERM_BITS = 6;
+}
 
-  // rocketNBDCache parameters
+abstract trait RocketDcacheConstants extends TileConfigConstants with AddressConstants {
   val DCACHE_PORTS = 3
   val CPU_DATA_BITS = 64;
   val CPU_TAG_BITS = 9;
@@ -188,17 +216,10 @@ object Constants
   val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS;
   val NWAYS = 4
   require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
+}
 
-  // coherence parameters
+trait TileLinkSizeConstants extends RocketDcacheConstants {
-  val ENABLE_SHARING = true
-  val ENABLE_CLEAN_EXCLUSIVE = true
-
-  val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8 
-  val TILE_ID_BITS = log2Up(NTILES)+1
   val TILE_XACT_ID_BITS = log2Up(NMSHR)+3
-  val NGLOBAL_XACTS = 8
-  val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS)
-
   val X_INIT_TYPE_MAX_BITS = 2
   val X_INIT_WRITE_MASK_BITS = OFFSET_BITS
   val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS)
@@ -206,24 +227,21 @@ object Constants
   val X_REP_TYPE_MAX_BITS = 3
   val P_REQ_TYPE_MAX_BITS = 2
   val P_REP_TYPE_MAX_BITS = 3
+}
 
-  // external memory interface
+trait MemoryInterfaceConstants extends UncoreConstants with TileLinkSizeConstants {
   val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS)
   val MEM_DATA_BITS = 128
   val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS
+}  
 
+trait TLBConstants {
   val DTLB_ENTRIES = 16
   val ITLB_ENTRIES = 8;
   val VITLB_ENTRIES = 4
+}
 
-  val START_ADDR = 0x2000;
+trait VectorOpConstants {
-
-  val FPU_N = UFix(0, 1);
-  val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N;
-
-  val VEC_N = UFix(0, 1);
-  val VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N;
-
   val VEC_X = Bits("b??", 2).toUFix
   val VEC_FN_N = UFix(0, 2)
   val VEC_VL = UFix(1, 2)
@@ -246,7 +264,9 @@ object Constants
   val VIMM2_RS2 = UFix(0, 1)
   val VIMM2_ALU = UFix(1, 1)
   val VIMM2_X = UFix(0, 1)
+}
 
+trait ArbiterConstants {
   val DTLB_CPU = 0
   val DTLB_VEC = 1
   val DTLB_VPF = 2

rocket/src/main/scala/ctrl.scala

@@ -1,8 +1,7 @@
 package rocket
 
 import Chisel._
-import Node._;
+import Node._
-
 import Constants._
 import Instructions._
 import hwacha._

rocket/src/main/scala/ctrl_util.scala

@@ -1,7 +1,7 @@
 package rocket
 
 import Chisel._
-import Node._;
+import Node._
 
 class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component
 {

rocket/src/main/scala/dpath.scala

@@ -1,8 +1,7 @@
 package rocket
 
 import Chisel._
-import Node._;
+import Node._
-
 import Constants._
 import Instructions._
 import hwacha._

rocket/src/main/scala/dpath_alu.scala

@@ -1,8 +1,7 @@
 package rocket
 
 import Chisel._
-import Node._;
+import Node._
-
 import Constants._
 import Instructions._
 

rocket/src/main/scala/dpath_util.scala

@@ -1,9 +1,9 @@
 package rocket
 
-import Chisel._;
+import Chisel._
-import Node._;
+import Node._
-import Constants._;
+import Constants._
-import scala.math._;
+import scala.math._
 
 class ioDpathBTB extends Bundle()
 {

rocket/src/main/scala/dtlb.scala

@@ -1,10 +1,10 @@
 package rocket
 
-import Chisel._;
+import Chisel._
-import Node._;
+import Node._
-import Constants._;
+import Constants._
-import scala.math._;
 import hwacha._
+import scala.math._
 
 // ioDTLB_CPU also located in hwacha/src/vuVXU-Interface.scala
 // should keep them in sync

rocket/src/main/scala/htif.scala

@@ -1,8 +1,8 @@
 package rocket
 
 import Chisel._
-import Node._;
+import Node._
-import Constants._;
+import Constants._
 import uncore._
 
 class ioDebug extends Bundle

rocket/src/main/scala/icache.scala

@@ -1,10 +1,10 @@
 package rocket
 
-import Chisel._;
+import Chisel._
-import Node._;
+import Node._
-import Constants._;
+import Constants._
-import scala.math._;
 import uncore._
+import scala.math._
 
 // interface between I$ and pipeline/ITLB (32 bits wide)
 class ioImem extends Bundle

rocket/src/main/scala/instructions.scala

@@ -1,7 +1,8 @@
 package rocket
 
 import Chisel._
-import Node._;
+import Node._
+import Constants._
 
 object Instructions
 {

rocket/src/main/scala/itlb.scala

@@ -1,9 +1,9 @@
 package rocket
 
-import Chisel._;
+import Chisel._
-import Node._;
+import Node._
-import Constants._;
+import Constants._
-import scala.math._;
+import scala.math._
 
 class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
     val clear        = Bool(INPUT);

rocket/src/main/scala/memserdes.scala

@@ -3,8 +3,8 @@ package rocket
 import Chisel._
 import Node._
 import Constants._
-import scala.math._
 import uncore._
+import scala.math._
 
 class ioMemSerialized extends Bundle
 {

rocket/src/main/scala/package.scala

@@ -0,0 +1,29 @@
+package rocket
+import rocket.constants._
+
+import Chisel._
+import scala.math._
+
+//TODO: When compiler bug SI-5604 is fixed in 2.10, change object Constants to 
+//      package object rocket and remove import Constants._'s from other files
+object Constants extends HTIFConstants with
+  MemoryOpConstants with
+  PCRConstants with 
+  InterruptConstants with 
+  AddressConstants with
+  ArbiterConstants with 
+  VectorOpConstants with 
+  TLBConstants with 
+  ScalarOpConstants with
+  MemoryInterfaceConstants
+{
+  val HAVE_RVC = false
+  val HAVE_FPU = true
+  val HAVE_VEC = true
+
+  val MAX_THREADS = 
+      hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK
+
+  val START_ADDR = 0x2000
+
+}

rocket/src/main/scala/ptw.scala

@@ -1,9 +1,9 @@
 package rocket
 
-import Chisel._;
+import Chisel._
-import Node._;
+import Node._
-import Constants._;
+import Constants._
-import scala.math._;
+import scala.math._
 
 class ioHellaCacheArbiter(n: Int) extends Bundle
 {

rocket/src/main/scala/queues.scala

@@ -1,7 +1,8 @@
 package rocket
 
 import Chisel._
-import Node._;
+import Node._
+import Constants._
 
 class SkidBuffer[T <: Data](resetSignal: Bool = null)(data: => T) extends Component(resetSignal)
 {

rocket/src/main/scala/top.scala

@@ -1,19 +1,21 @@
 package rocket
 
 import Chisel._
-import Node._;
+import Node._
+import Constants._
 import uncore._
-import Constants._;
 import collection.mutable.ArrayBuffer
 
+object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants {
+//  val NTILES = 1
+  val ENABLE_SHARING = true
+  val ENABLE_CLEAN_EXCLUSIVE = true
+}
+import DummyTopLevelConstants._
+
+
 class Top extends Component 
 {
-  val io = new Bundle  {
-    val debug   = new ioDebug
-    val host    = new ioHost(HTIF_WIDTH)
-    val mem     = new ioMemPipe
-  }
-
   val co =  if(ENABLE_SHARING) {
               if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
               else new MSICoherence
@@ -22,6 +24,12 @@ class Top extends Component
               else new MICoherence
             }
 
+  val io = new Bundle  {
+    val debug   = new ioDebug
+    val host    = new ioHost(HTIF_WIDTH)
+    val mem     = new ioMemPipe
+  }
+
   val htif = new rocketHTIF(HTIF_WIDTH, NTILES, co)
   val hub = new CoherenceHubBroadcast(NTILES+1, co)
   hub.io.tiles(NTILES) <> htif.io.mem

rocket/src/main/scala/util.scala

@@ -1,8 +1,6 @@
 package rocket
 
 import Chisel._
-import Node._
-import scala.math._
 
 class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
 {