riscv/rocket-chip
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rocket: invoke LazyModule at point of use/binding

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This commit is contained in:
Wesley W. Terpstra 2017-09-12 12:10:39 -07:00
parent 87d597c70d
commit dfc815f4d3
2 changed files with 4 additions and 4 deletions
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3
src/main/scala/groundtest/Tile.scala
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@ -5,6 +5,7 @@ package freechips.rocketchip.groundtest
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.coreplex._
import freechips.rocketchip.rocket.{HellaCache, RocketCoreParams}
import freechips.rocketchip.tile._
@ -29,7 +30,7 @@ case object GroundTestTilesKey extends Field[Seq[GroundTestTileParams]]
abstract class GroundTestTile(params: GroundTestTileParams)(implicit p: Parameters) extends BaseTile(params)(p) {
val slave = None
val dcacheOpt = params.dcache.map { dc => HellaCache(0, dc.nMSHRs == 0) }
val dcacheOpt = params.dcache.map { dc => LazyModule(HellaCache(0, dc.nMSHRs == 0)) }
dcacheOpt.foreach { tileBus.node := _.node }
override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this))

5
src/main/scala/rocket/HellaCache.scala
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@ -195,8 +195,7 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
object HellaCache {
def apply(hartid: Int, blocking: Boolean, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = {
if (blocking) LazyModule(new DCache(hartid, scratch))
else LazyModule(new NonBlockingDCache(hartid))
if (blocking) new DCache(hartid, scratch) else new NonBlockingDCache(hartid)
}
}
@ -208,7 +207,7 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
def findScratchpadFromICache: Option[AddressSet]
val hartid: Int
var nDCachePorts = 0
val dcache = HellaCache(hartid, tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
val dcache = LazyModule(HellaCache(hartid, tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _))
tileBus.node := dcache.node
}