riscv/rocket-chip
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use assert, not Assert

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This commit is contained in:
Andrew Waterman 2013-05-18 00:45:13 -07:00
parent d405ffa949
commit dfa7a03f73
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/icache.scala
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@ -172,7 +172,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
val s2_miss = s2_valid && !s2_any_tag_hit val s2_miss = s2_valid && !s2_any_tag_hit
rdy := state === s_ready && !s2_miss rdy := state === s_ready && !s2_miss
Assert(!c.co.isVoluntary(io.mem.grant.bits.payload) || !io.mem.grant.valid, "UncachedRequestors shouldn't get voluntary grants.") assert(!c.co.isVoluntary(io.mem.grant.bits.payload) || !io.mem.grant.valid, "UncachedRequestors shouldn't get voluntary grants.")
val (rf_cnt, refill_done) = Counter(io.mem.grant.valid, REFILL_CYCLES) val (rf_cnt, refill_done) = Counter(io.mem.grant.valid, REFILL_CYCLES)
val repl_way = if (c.dm) UFix(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0) val repl_way = if (c.dm) UFix(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0)