From df32cc388726fbdaf17b99a84c01171c5f12e6c9 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sun, 4 Sep 2016 17:48:45 -0700 Subject: [PATCH] tilelink2: be careful; apply Andrew's masking trick everywhere --- src/main/scala/uncore/tilelink2/Legacy.scala | 2 +- src/main/scala/uncore/tilelink2/Parameters.scala | 8 ++++---- src/main/scala/uncore/tilelink2/TLNodes.scala | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Legacy.scala b/src/main/scala/uncore/tilelink2/Legacy.scala index e4b8b2b2..ed051ae6 100644 --- a/src/main/scala/uncore/tilelink2/Legacy.scala +++ b/src/main/scala/uncore/tilelink2/Legacy.scala @@ -82,7 +82,7 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa // Get rid of some unneeded muxes out.a.bits.source := source out.a.bits.data := data - out.a.bits.address := address & ~addressMask + out.a.bits.address := ~(~address | addressMask) // TL legacy does not support bus errors assert (!out.d.bits.error) diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 26e799ec..138ff9a5 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -33,8 +33,8 @@ case class IdRange(start: Int, end: Int) def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (start+1 == end) { UInt(start) === x } - else if (((end-1) & ~start) == end-start-1) - { ((UInt(start) ^ x) & ~UInt(end-start-1)) === UInt(0) } + else if (isPow2(end-start) && ((end | start) & (end-start-1)) == 0) + { ~(~(UInt(start) ^ x) | UInt(end-start-1)) === UInt(0) } else { UInt(start) <= x && x < UInt(end) } def shift(x: Int) = IdRange(start+x, end+x) @@ -84,8 +84,8 @@ case class AddressSet(base: BigInt, mask: BigInt) // Forbid misaligned base address (and empty sets) require ((base & mask) == 0) - def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 - def contains(x: UInt) = ((x ^ UInt(base)) & ~UInt(mask)) === UInt(0) + def contains(x: BigInt) = ~(~(x ^ base) | mask) == 0 + def contains(x: UInt) = ~(~(x ^ UInt(base)) | UInt(mask)) === UInt(0) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 diff --git a/src/main/scala/uncore/tilelink2/TLNodes.scala b/src/main/scala/uncore/tilelink2/TLNodes.scala index 05353cdc..f9685a0a 100644 --- a/src/main/scala/uncore/tilelink2/TLNodes.scala +++ b/src/main/scala/uncore/tilelink2/TLNodes.scala @@ -23,10 +23,10 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL require (eo.asInstanceOf[TLEdgeParameters] == ei.asInstanceOf[TLEdgeParameters]) TLMonitor.legalize(bo, eo, bi, ei) bi <> bo - val mask = ~UInt(ei.manager.beatBytes - 1) - bi.a.bits.address := (mask & bo.a.bits.address) - bo.b.bits.address := (mask & bi.b.bits.address) - bi.c.bits.address := (mask & bo.c.bits.address) + val mask = UInt(ei.manager.beatBytes - 1) + bi.a.bits.address := ~(mask | ~bo.a.bits.address) + bo.b.bits.address := ~(mask | ~bi.b.bits.address) + bi.c.bits.address := ~(mask | ~bo.c.bits.address) } }