BuildTiles: convert to LazyTile

src/main/scala/coreplex/BaseCoreplex.scala

@@ -23,7 +23,7 @@ case object BankIdLSB extends Field[Int]
 /** Function for building some kind of coherence manager agent */
 case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
 /** Function for building some kind of tile connected to a reset signal */
-case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
+case object BuildTiles extends Field[Seq[Parameters => LazyTile]]
 /** The file to read the BootROM contents from */
 case object BootROMFile extends Field[String]
 
@@ -49,6 +49,7 @@ case class CoreplexConfig(
 }
 
 abstract class BaseCoreplex(c: CoreplexConfig)(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
+  val lazyTiles = p(BuildTiles) map { _(p) }
 
   val debugLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
   val debug = LazyModule(new TLDebugModule())
@@ -89,7 +90,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
   val io: B = b
 
   // Build a set of Tiles
-  val tiles = p(BuildTiles) map { _(reset, p) }
+  val tiles = outer.lazyTiles.map(_.module)
   val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }
 
   val nCachedPorts = tiles.map(tile => tile.io.cached.size).reduce(_ + _)

src/main/scala/coreplex/Configs.scala

@@ -4,6 +4,7 @@ package coreplex
 
 import Chisel._
 import junctions._
+import diplomacy._
 import uncore.tilelink._
 import uncore.coherence._
 import uncore.agents._
@@ -69,8 +70,8 @@ class BaseCoreplexConfig extends Config (
       case NUncachedTileLinkPorts => 1
       //Tile Constants
       case BuildTiles => {
-        List.tabulate(site(NTiles)){ i => (r: Bool, p: Parameters) =>
+        List.tabulate(site(NTiles)){ i => (p: Parameters) =>
-          Module(new RocketTile(resetSignal = r)(p.alterPartial({
+          LazyModule(new RocketTile()(p.alterPartial({
             case TileId => i
             case TLId => "L1toL2"
             case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels)

src/main/scala/coreplex/Coreplex.scala

@@ -9,7 +9,7 @@ import util._
 import rocket._
 
 trait DirectConnection {
-  val tiles: Seq[Tile]
+  val tiles: Seq[TileImp]
   val uncoreTileIOs: Seq[TileIO]
 
   val tlBuffering = TileLinkDepths(1,1,2,2,0)
@@ -49,7 +49,7 @@ trait TileClockResetBundle {
 
 trait AsyncConnection {
   val io: TileClockResetBundle
-  val tiles: Seq[Tile]
+  val tiles: Seq[TileImp]
   val uncoreTileIOs: Seq[TileIO]
 
   (tiles, uncoreTileIOs, io.tcrs).zipped foreach { case (tile, uncore, tcr) =>

src/main/scala/groundtest/Configs.scala

@@ -95,8 +95,8 @@ class WithGroundTest extends Config(
     case BuildTiles => {
       (0 until site(NTiles)).map { i =>
         val tileSettings = site(GroundTestKey)(i)
-        (r: Bool, p: Parameters) => {
+        (p: Parameters) => {
-          Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
+          LazyModule(new GroundTestTile()(p.alterPartial({
             case TLId => "L1toL2"
             case TileId => i
             case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0

src/main/scala/groundtest/Tile.scala

@@ -96,12 +96,9 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
   val io = new GroundTestIO
 }
 
-class GroundTestTile(resetSignal: Bool)
+class GroundTestTile(implicit val p: Parameters) extends LazyTile with HasGroundTestParameters {
-                    (implicit val p: Parameters)
+  lazy val module = new TileImp(this) {
-                    extends Tile(resetSignal = resetSignal)(p)
+    val io = new TileIO(bc) {
-                    with HasGroundTestParameters {
-
-  override val io = new TileIO(bc) {
       val success = Bool(OUTPUT)
     }
 
@@ -140,4 +137,5 @@ class GroundTestTile(resetSignal: Bool)
     }
 
     io.success := test.io.status.finished
+  }
 }

src/main/scala/rocket/tile.scala

@@ -3,7 +3,9 @@
 package rocket
 
 import Chisel._
+import diplomacy._
 import uncore.tilelink._
+import uncore.tilelink2._
 import uncore.agents._
 import uncore.converters._
 import uncore.devices._
@@ -39,8 +41,7 @@ class TileIO(c: TileBundleConfig)(implicit p: Parameters) extends Bundle {
   override def cloneType = new TileIO(c).asInstanceOf[this.type]
 }
 
-abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null)
+abstract class TileImp(l: LazyTile)(implicit p: Parameters) extends LazyModuleImp(l) {
-    (implicit p: Parameters) extends Module(Option(clockSignal), Option(resetSignal)) {
   val nCachedTileLinkPorts = p(NCachedTileLinkPorts)
   val nUncachedTileLinkPorts = p(NUncachedTileLinkPorts)
   val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
@@ -50,11 +51,16 @@ abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null)
     xLen = p(XLen),
     hasSlavePort = p(DataScratchpadSize) > 0)
 
-  val io = new TileIO(bc)
+  val io: TileIO
 }
 
-class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
+abstract class LazyTile(implicit p: Parameters) extends LazyModule {
-    (implicit p: Parameters) extends Tile(clockSignal, resetSignal)(p) {
+  val module: TileImp
+}
+
+class RocketTile(implicit p: Parameters) extends LazyTile {
+  lazy val module = new TileImp(this) {
+    val io = new TileIO(bc)
     val buildRocc = p(BuildRoCC)
     val usingRocc = !buildRocc.isEmpty
     val nRocc = buildRocc.size
@@ -157,4 +163,5 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
         fpu.io.cp_resp.ready := Bool(false)
       }
     }
+  }
 }