BuildTiles: convert to LazyTile
This commit is contained in:
Wesley W. Terpstra
@ -3,7 +3,9 @@
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package rocket
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import Chisel._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.agents._
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import uncore.converters._
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import uncore.devices._
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@ -39,8 +41,7 @@ class TileIO(c: TileBundleConfig)(implicit p: Parameters) extends Bundle {
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override def cloneType = new TileIO(c).asInstanceOf[this.type]
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}
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abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null)
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(implicit p: Parameters) extends Module(Option(clockSignal), Option(resetSignal)) {
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abstract class TileImp(l: LazyTile)(implicit p: Parameters) extends LazyModuleImp(l) {
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val nCachedTileLinkPorts = p(NCachedTileLinkPorts)
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val nUncachedTileLinkPorts = p(NUncachedTileLinkPorts)
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val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
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@ -50,111 +51,117 @@ abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null)
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xLen = p(XLen),
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hasSlavePort = p(DataScratchpadSize) > 0)
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val io = new TileIO(bc)
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val io: TileIO
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}
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class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
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(implicit p: Parameters) extends Tile(clockSignal, resetSignal)(p) {
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val buildRocc = p(BuildRoCC)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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val nFPUPorts = buildRocc.filter(_.useFPU).size
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abstract class LazyTile(implicit p: Parameters) extends LazyModule {
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val module: TileImp
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}
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val core = Module(new Rocket)
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val icache = Module(new Frontend()(p.alterPartial({ case CacheName => "L1I" })))
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val dcache = HellaCache(p(DCacheKey))(dcacheParams)
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class RocketTile(implicit p: Parameters) extends LazyTile {
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lazy val module = new TileImp(this) {
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val io = new TileIO(bc)
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val buildRocc = p(BuildRoCC)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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val nFPUPorts = buildRocc.filter(_.useFPU).size
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val ptwPorts = collection.mutable.ArrayBuffer(icache.io.ptw, dcache.ptw)
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val dcPorts = collection.mutable.ArrayBuffer(core.io.dmem)
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val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
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val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
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val cachedPorts = collection.mutable.ArrayBuffer(dcache.mem)
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core.io.interrupts := io.interrupts
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core.io.hartid := io.hartid
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icache.io.cpu <> core.io.imem
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icache.io.resetVector := io.resetVector
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val core = Module(new Rocket)
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val icache = Module(new Frontend()(p.alterPartial({ case CacheName => "L1I" })))
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val dcache = HellaCache(p(DCacheKey))(dcacheParams)
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val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)))
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fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
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val ptwPorts = collection.mutable.ArrayBuffer(icache.io.ptw, dcache.ptw)
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val dcPorts = collection.mutable.ArrayBuffer(core.io.dmem)
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val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
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val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
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val cachedPorts = collection.mutable.ArrayBuffer(dcache.mem)
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core.io.interrupts := io.interrupts
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core.io.hartid := io.hartid
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icache.io.cpu <> core.io.imem
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icache.io.resetVector := io.resetVector
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if (usingRocc) {
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val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
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core.io.rocc.resp <> respArb.io.out
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val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)))
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fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
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val roccOpcodes = buildRocc.map(_.opcodes)
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val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
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cmdRouter.io.in <> core.io.rocc.cmd
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if (usingRocc) {
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val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
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core.io.rocc.resp <> respArb.io.out
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val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
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val rocc = accelParams.generator(p.alterPartial({
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case RoccNMemChannels => accelParams.nMemChannels
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case RoccNPTWPorts => accelParams.nPTWPorts
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}))
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val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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rocc.io.cmd <> cmdRouter.io.out(i)
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rocc.io.exception := core.io.rocc.exception
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dcIF.io.requestor <> rocc.io.mem
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dcPorts += dcIF.io.cache
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uncachedArbPorts += rocc.io.autl
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rocc
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val roccOpcodes = buildRocc.map(_.opcodes)
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val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
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cmdRouter.io.in <> core.io.rocc.cmd
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val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
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val rocc = accelParams.generator(p.alterPartial({
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case RoccNMemChannels => accelParams.nMemChannels
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case RoccNPTWPorts => accelParams.nPTWPorts
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}))
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val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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rocc.io.cmd <> cmdRouter.io.out(i)
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rocc.io.exception := core.io.rocc.exception
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dcIF.io.requestor <> rocc.io.mem
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dcPorts += dcIF.io.cache
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uncachedArbPorts += rocc.io.autl
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rocc
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}
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if (nFPUPorts > 0) {
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fpuOpt.foreach { fpu =>
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val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts))
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val fp_roccs = roccs.zip(buildRocc)
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.filter { case (_, params) => params.useFPU }
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.map { case (rocc, _) => rocc.io }
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fpArb.io.in_req <> fp_roccs.map(_.fpu_req)
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fp_roccs.zip(fpArb.io.in_resp).foreach {
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case (rocc, fpu_resp) => rocc.fpu_resp <> fpu_resp
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}
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fpu.io.cp_req <> fpArb.io.out_req
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fpArb.io.out_resp <> fpu.io.cp_resp
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}
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}
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core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
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core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
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respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
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ptwPorts ++= roccs.flatMap(_.io.ptw)
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uncachedPorts ++= roccs.flatMap(_.io.utl)
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}
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if (nFPUPorts > 0) {
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val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size))
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uncachedArb.io.in <> uncachedArbPorts
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uncachedArb.io.out +=: uncachedPorts
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// Connect the caches and RoCC to the outer memory system
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io.uncached <> uncachedPorts
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io.cached <> cachedPorts
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// TODO remove nCached/nUncachedTileLinkPorts parameters and these assertions
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require(uncachedPorts.size == nUncachedTileLinkPorts)
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require(cachedPorts.size == nCachedTileLinkPorts)
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if (p(UseVM)) {
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val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
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ptw.io.requestor <> ptwPorts
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ptw.io.mem +=: dcPorts
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core.io.ptw <> ptw.io.dpath
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}
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io.slave foreach { case slavePort =>
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val adapter = Module(new ScratchpadSlavePort()(dcacheParams))
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adapter.io.tl <> TileLinkFragmenter(slavePort)
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adapter.io.dmem +=: dcPorts
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}
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require(dcPorts.size == core.dcacheArbPorts)
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val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
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dcArb.io.requestor <> dcPorts
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dcache.cpu <> dcArb.io.mem
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if (nFPUPorts == 0) {
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fpuOpt.foreach { fpu =>
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val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts))
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val fp_roccs = roccs.zip(buildRocc)
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.filter { case (_, params) => params.useFPU }
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.map { case (rocc, _) => rocc.io }
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fpArb.io.in_req <> fp_roccs.map(_.fpu_req)
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fp_roccs.zip(fpArb.io.in_resp).foreach {
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case (rocc, fpu_resp) => rocc.fpu_resp <> fpu_resp
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}
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fpu.io.cp_req <> fpArb.io.out_req
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fpArb.io.out_resp <> fpu.io.cp_resp
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fpu.io.cp_req.valid := Bool(false)
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fpu.io.cp_resp.ready := Bool(false)
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}
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}
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core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
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core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
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respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
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ptwPorts ++= roccs.flatMap(_.io.ptw)
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uncachedPorts ++= roccs.flatMap(_.io.utl)
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}
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val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size))
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uncachedArb.io.in <> uncachedArbPorts
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uncachedArb.io.out +=: uncachedPorts
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// Connect the caches and RoCC to the outer memory system
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io.uncached <> uncachedPorts
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io.cached <> cachedPorts
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// TODO remove nCached/nUncachedTileLinkPorts parameters and these assertions
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require(uncachedPorts.size == nUncachedTileLinkPorts)
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require(cachedPorts.size == nCachedTileLinkPorts)
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if (p(UseVM)) {
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val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
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ptw.io.requestor <> ptwPorts
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ptw.io.mem +=: dcPorts
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core.io.ptw <> ptw.io.dpath
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}
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io.slave foreach { case slavePort =>
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val adapter = Module(new ScratchpadSlavePort()(dcacheParams))
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adapter.io.tl <> TileLinkFragmenter(slavePort)
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adapter.io.dmem +=: dcPorts
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}
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require(dcPorts.size == core.dcacheArbPorts)
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val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
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dcArb.io.requestor <> dcPorts
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dcache.cpu <> dcArb.io.mem
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if (nFPUPorts == 0) {
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fpuOpt.foreach { fpu =>
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fpu.io.cp_req.valid := Bool(false)
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fpu.io.cp_resp.ready := Bool(false)
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}
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}
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}
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