riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

BuildTiles: convert to LazyTile

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-10-26 19:02:04 -07:00
parent f8a0829134
commit dddb50a942
6 changed files with 150 additions and 143 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/coreplex/Coreplex.scala
View File

@ -9,7 +9,7 @@ import util._
import rocket._
trait DirectConnection {
val tiles: Seq[Tile]
val tiles: Seq[TileImp]
val uncoreTileIOs: Seq[TileIO]
val tlBuffering = TileLinkDepths(1,1,2,2,0)
@ -49,7 +49,7 @@ trait TileClockResetBundle {
trait AsyncConnection {
val io: TileClockResetBundle
val tiles: Seq[Tile]
val tiles: Seq[TileImp]
val uncoreTileIOs: Seq[TileIO]
(tiles, uncoreTileIOs, io.tcrs).zipped foreach { case (tile, uncore, tcr) =>