BuildTiles: convert to LazyTile

src/main/scala/coreplex/BaseCoreplex.scala

@@ -23,7 +23,7 @@ case object BankIdLSB extends Field[Int]
 /** Function for building some kind of coherence manager agent */
 case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
 /** Function for building some kind of tile connected to a reset signal */
-case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
+case object BuildTiles extends Field[Seq[Parameters => LazyTile]]
 /** The file to read the BootROM contents from */
 case object BootROMFile extends Field[String]
 
@@ -49,6 +49,7 @@ case class CoreplexConfig(
 }
 
 abstract class BaseCoreplex(c: CoreplexConfig)(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
+  val lazyTiles = p(BuildTiles) map { _(p) }
 
   val debugLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
   val debug = LazyModule(new TLDebugModule())
@@ -89,7 +90,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
   val io: B = b
 
   // Build a set of Tiles
-  val tiles = p(BuildTiles) map { _(reset, p) }
+  val tiles = outer.lazyTiles.map(_.module)
   val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }
 
   val nCachedPorts = tiles.map(tile => tile.io.cached.size).reduce(_ + _)

src/main/scala/coreplex/Configs.scala

@@ -4,6 +4,7 @@ package coreplex
 
 import Chisel._
 import junctions._
+import diplomacy._
 import uncore.tilelink._
 import uncore.coherence._
 import uncore.agents._
@@ -69,8 +70,8 @@ class BaseCoreplexConfig extends Config (
       case NUncachedTileLinkPorts => 1
       //Tile Constants
       case BuildTiles => {
-        List.tabulate(site(NTiles)){ i => (r: Bool, p: Parameters) =>
-          Module(new RocketTile(resetSignal = r)(p.alterPartial({
+        List.tabulate(site(NTiles)){ i => (p: Parameters) =>
+          LazyModule(new RocketTile()(p.alterPartial({
             case TileId => i
             case TLId => "L1toL2"
             case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels)

src/main/scala/coreplex/Coreplex.scala

@@ -9,7 +9,7 @@ import util._
 import rocket._
 
 trait DirectConnection {
-  val tiles: Seq[Tile]
+  val tiles: Seq[TileImp]
   val uncoreTileIOs: Seq[TileIO]
 
   val tlBuffering = TileLinkDepths(1,1,2,2,0)
@@ -49,7 +49,7 @@ trait TileClockResetBundle {
 
 trait AsyncConnection {
   val io: TileClockResetBundle
-  val tiles: Seq[Tile]
+  val tiles: Seq[TileImp]
   val uncoreTileIOs: Seq[TileIO]
 
   (tiles, uncoreTileIOs, io.tcrs).zipped foreach { case (tile, uncore, tcr) =>