riscv/rocket-chip
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Avoid need for cloneType

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This commit is contained in:
Andrew Waterman 2016-06-05 23:47:56 -07:00
parent 631e3e2dd9
commit dd85f2410f
1 changed files with 9 additions and 11 deletions
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20
uncore/src/main/scala/prci.scala
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@ -11,15 +11,18 @@ import cde.{Parameters, Field}
/** Number of tiles */ /** Number of tiles */
case object NTiles extends Field[Int] case object NTiles extends Field[Int]
class PRCIInterrupts extends Bundle {
val mtip = Bool()
val meip = Bool()
val seip = Bool()
val debug = Bool()
}
class PRCITileIO(implicit p: Parameters) extends Bundle { class PRCITileIO(implicit p: Parameters) extends Bundle {
val reset = Bool(OUTPUT) val reset = Bool(OUTPUT)
val id = UInt(OUTPUT, log2Up(p(NTiles))) val id = UInt(OUTPUT, log2Up(p(NTiles)))
val interrupts = new Bundle { val interrupts = new PRCIInterrupts {
val mtip = Bool()
val msip = Bool() val msip = Bool()
val meip = Bool()
val seip = Bool()
val debug = Bool()
}.asOutput }.asOutput
override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type] override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type]
@ -30,12 +33,7 @@ class PRCI(implicit val p: Parameters) extends Module
with HasTileLinkParameters with HasTileLinkParameters
with HasAddrMapParameters { with HasAddrMapParameters {
val io = new Bundle { val io = new Bundle {
val interrupts = Vec(p(NTiles), new Bundle { val interrupts = Vec(p(NTiles), new PRCIInterrupts).asInput
val mtip = Bool()
val meip = Bool()
val seip = Bool()
val debug = Bool()
}).asInput
val tl = new ClientUncachedTileLinkIO().flip val tl = new ClientUncachedTileLinkIO().flip
val tiles = Vec(p(NTiles), new PRCITileIO) val tiles = Vec(p(NTiles), new PRCITileIO)
} }