Add JTAG DTM and test support in simulation

Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box

vsim/Makefrag

@@ -4,16 +4,22 @@
 
 # Verilog sources
 
+bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
+	   $(base_dir)/vsrc/jtag_vpi.v \
+	   $(base_dir)/vsrc/AsyncMailbox.v
+
 sim_vsrcs = \
 	$(generated_dir)/$(MODEL).$(CONFIG).v \
 	$(generated_dir)/consts.$(CONFIG).vh \
-	$(base_dir)/vsrc/$(TB).v \
+        $(base_dir)/vsrc/$(TB).v \
 	$(base_dir)/vsrc/SimDTM.v \
+	$(bb_vsrcs)
 
 # C sources
 
 sim_csrcs = \
 	$(base_dir)/csrc/SimDTM.cc \
+	$(base_dir)/csrc/jtag_vpi.c
 
 #--------------------------------------------------------------------
 # Build Verilog
@@ -45,6 +51,11 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	+define+RANDOMIZE \
 	+libext+.v \
 
+VCS_OPTS += +vpi
+VCS_OPTS += -P $(base_dir)/vsrc/jtag_vpi.tab
+VCS_OPTS += -CC "-DVCS_VPI"
+
+
 #--------------------------------------------------------------------
 # Build the simulator
 #--------------------------------------------------------------------