Add JTAG DTM and test support in simulation

Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box

src/main/scala/uncore/devices/Debug.scala

@@ -8,7 +8,7 @@ import uncore.util._
 import junctions._
 import cde.{Parameters, Config, Field}
 
-// *****************************************
+// *****************************************r
 // Constants which are interesting even
 // outside of this module
 // *****************************************
@@ -264,7 +264,7 @@ class DefaultDebugModuleConfig (val ncomponents : Int, val xlen:Int)
       nNDResetCycles = 1)
 
 case object DMKey extends Field[DebugModuleConfig]
-
+case object IncludeJtagDTM extends Field[Boolean]
 
 // *****************************************
 // Module Interfaces
@@ -277,8 +277,8 @@ case object DMKey extends Field[DebugModuleConfig]
 
 class DebugBusReq(addrBits : Int) extends Bundle {
   val addr = UInt(width = addrBits)
-  val op   = UInt(width = DbBusConsts.dbOpSize)
   val data = UInt(width = DbBusConsts.dbDataSize)
+  val op   = UInt(width = DbBusConsts.dbOpSize)
 
   override def cloneType = new DebugBusReq(addrBits).asInstanceOf[this.type]
 }
@@ -287,8 +287,9 @@ class DebugBusReq(addrBits : Int) extends Bundle {
 /** Structure to define the contents of a Debug Bus Response
   */
 class DebugBusResp( ) extends Bundle {
-  val resp = UInt(width = DbBusConsts.dbRespSize)
   val data = UInt(width = DbBusConsts.dbDataSize)
+  val resp = UInt(width = DbBusConsts.dbRespSize)
+
 }
 
 /** Structure to define the top-level DebugBus interface 
@@ -999,3 +1000,5 @@ object AsyncDebugBusTo { // OutsideClockDomain
     sink
   }
 }
+
+