Add JTAG DTM and test support in simulation
Initial cut checkpoint which compiles and runs but there is some off-by-1 in the protocol Debugging the clock crossing logic checkpoint which works Clean up the AsyncMailbox black box
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@ -122,6 +122,7 @@ class BasePlatformConfig extends Config (
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case BuildCoreplex => (p: Parameters) => Module(new DefaultCoreplex(p))
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case NExtInterrupts => 2
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case AsyncDebugBus => false
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case IncludeJtagDTM => false
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case AsyncMMIOChannels => false
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case ExtraDevices => Nil
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case ExtraTopPorts => (p: Parameters) => new Bundle
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@ -277,4 +278,18 @@ class WithTestRAM extends Config(
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}
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Seq(new TestRAMDevice)
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}
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})
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}
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)
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class WithAsyncDebug extends Config (
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(pname, site, here) => pname match {
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case AsyncDebugBus => true
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}
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)
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class WithJtagDTM extends Config (
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(pname, site, here) => pname match {
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case IncludeJtagDTM => true
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}
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)
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@ -87,9 +87,10 @@ class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
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val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
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val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(outermostMMIOParams))
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val debug_clk = if (p(AsyncDebugBus)) Some(Clock(INPUT)) else None
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val debug_rst = if (p(AsyncDebugBus)) Some(Bool(INPUT)) else None
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val debug = new DebugBusIO()(p).flip
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val debug_clk = if (p(AsyncDebugBus) & !p(IncludeJtagDTM)) Some(Clock(INPUT)) else None
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val debug_rst = if (p(AsyncDebugBus) & !p(IncludeJtagDTM)) Some(Bool(INPUT)) else None
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val debug = if (!p(IncludeJtagDTM)) Some(new DebugBusIO()(p).flip) else None
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val jtag = if ( p(IncludeJtagDTM)) Some(new JtagIO(true).flip) else None
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val extra = p(ExtraTopPorts)(p)
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}
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@ -137,10 +138,18 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
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periphery.io.mem_in <> coreplex.io.mem
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coreplex.io.ext_clients <> periphery.io.clients_out
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coreplex.io.debug <>
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if (p(IncludeJtagDTM)) {
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// JtagDTMWithSync is a wrapper which
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// handles the synchronization as well.
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val jtag_dtm = Module (new JtagDTMWithSync()(p))
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jtag_dtm.io.jtag <> io.jtag.get
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coreplex.io.debug <> jtag_dtm.io.debug
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} else {
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coreplex.io.debug <>
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(if (p(AsyncDebugBus))
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AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug)
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else io.debug)
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AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug.get)
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else io.debug.get)
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}
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def asyncAxiTo(clocks: Seq[Clock], resets: Seq[Bool], inner_axis: Seq[NastiIO]): Seq[NastiIO] =
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(clocks, resets, inner_axis).zipped.map {
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@ -6,6 +6,7 @@ import Chisel._
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import cde.{Parameters, Field}
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import rocket.Util._
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import junctions._
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import uncore.devices.{IncludeJtagDTM}
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class TestHarness(implicit p: Parameters) extends Module {
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val io = new Bundle {
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@ -26,9 +27,6 @@ class TestHarness(implicit p: Parameters) extends Module {
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require(dut.io.mmio_axi.isEmpty)
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require(dut.io.mmio_ahb.isEmpty)
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require(dut.io.mmio_tl.isEmpty)
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require(dut.io.debug_clk.isEmpty)
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require(dut.io.debug_rst.isEmpty)
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require(dut.io.debug_rst.isEmpty)
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require(dut.io.extra.elements.isEmpty)
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for (int <- dut.io.interrupts)
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@ -41,14 +39,42 @@ class TestHarness(implicit p: Parameters) extends Module {
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Module(new SimAXIMem(memSize / dut.io.mem_axi.size)).io.axi <> axi
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}
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val dtm = Module(new SimDTM)
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dut.io.debug <> dtm.io.debug
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dtm.io.clk := clock
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dtm.io.reset := reset
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io.success := dut.io.success.getOrElse(dtm.io.exit === 1)
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when (dtm.io.exit >= 2) {
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printf("*** FAILED *** (exit code = %d)\n", dtm.io.exit >> 1)
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stop(1)
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if (p(IncludeJtagDTM)) {
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val jtag_vpi = Module (new JtagVpi)
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dut.io.jtag.get <> jtag_vpi.io.jtag
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// To be proper,
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// TRST should really be synchronized
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// with TCK. But this is a fairly
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// accurate representation of how
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// HW may drive this signal.
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// Neither OpenOCD nor JtagVPI drive TRST.
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dut.io.jtag.get.TRST := reset
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jtag_vpi.io.enable := ~reset
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jtag_vpi.io.init_done := ~reset
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io.success := Bool(false)
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}
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else {
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val dtm = Module(new SimDTM)
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dut.io.debug.get <> dtm.io.debug
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// Todo: enable the usage of different clocks.
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val dtm_clock = clock
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val dtm_reset = reset
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dtm.io.clk := dtm_clock
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dtm.io.reset := dtm_reset
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if (dut.io.debug_clk.isDefined)
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dut.io.debug_clk.get := dtm_clock
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if (dut.io.debug_rst.isDefined)
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dut.io.debug_rst.get := dtm_reset
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io.success := dut.io.success.getOrElse(dtm.io.exit === 1)
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when (dtm.io.exit >= 2) {
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printf("*** FAILED *** (exit code = %d)\n", dtm.io.exit >> 1)
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stop(1)
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}
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}
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}
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@ -114,3 +140,13 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
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val exit = UInt(OUTPUT, 32)
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}
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}
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class JtagVpi(implicit val p: Parameters) extends BlackBox {
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val io = new Bundle {
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val jtag = new JtagIO(false)
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val enable = Bool(INPUT)
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val init_done = Bool(INPUT)
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}
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}
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