riscv/rocket-chip
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BusBypass: only stall A once the last beat is accepted ()

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When switching ports, the bypass stalls new messages until all
outstanding messages have received their responses. However, this
stall must NOT stop the remaining beats of a partially sent request.
This commit is contained in:
Wesley W. Terpstra 2017-11-06 11:13:15 -08:00 committed by GitHub
parent 7e75d63ba6
commit dcf67b49fa
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1 changed files with 1 additions and 1 deletions

2
src/main/scala/devices/tilelink/BusBypass.scala

@ -93,7 +93,7 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule
flight := next_flight flight := next_flight
when (next_flight === UInt(0)) { bypass := io.bypass } when (next_flight === UInt(0)) { bypass := io.bypass }
val stall = bypass != io.bypass val stall = (bypass != io.bypass) && a_first
out0.a.valid := !stall && in.a.valid && bypass out0.a.valid := !stall && in.a.valid && bypass
out1.a.valid := !stall && in.a.valid && !bypass out1.a.valid := !stall && in.a.valid && !bypass