get multichannel simulation working in emulator

src/main/scala/Configs.scala

@@ -280,3 +280,5 @@ class ExampleSmallConfig extends Config(new SmallConfig ++ new DefaultConfig)
 class MultibankConfig extends Config(new With2Banks ++ new DefaultConfig)
 class MultibankL2Config extends Config(
   new With2Banks ++ new WithL2Cache ++ new DefaultConfig)
+
+class MultichannelConfig extends Config(new With2MemoryChannels ++ new DefaultConfig)

src/main/scala/TestBench.scala

@@ -5,7 +5,7 @@ package rocketchip
 import Chisel._
 
 object TestBenchGeneration extends FileSystemUtilities {
-  def generateVerilogFragement(
+  def generateVerilogFragment(
     topModuleName: String, configClassName: String,
     nMemChannel: Int) = {
 
@@ -322,4 +322,47 @@ object TestBenchGeneration extends FileSystemUtilities {
     f.write(defs + nasti_defs + delays + nasti_delays + instantiation + ticks)
     f.close
   }
+
+  def generateCPPFragment(
+      topModuleName: String, configClassName: String, nMemChannel: Int) {
+
+    val assigns = (0 until nMemChannel).map { i => s"""
+      mem_ar_valid[$i] = &tile.Top__io_mem_${i}_ar_valid;
+      mem_ar_ready[$i] = &tile.Top__io_mem_${i}_ar_ready;
+      mem_ar_bits_addr[$i] = &tile.Top__io_mem_${i}_ar_bits_addr;
+      mem_ar_bits_id[$i] = &tile.Top__io_mem_${i}_ar_bits_id;
+      mem_ar_bits_size[$i] = &tile.Top__io_mem_${i}_ar_bits_size;
+      mem_ar_bits_len[$i] = &tile.Top__io_mem_${i}_ar_bits_len;
+
+      mem_aw_valid[$i] = &tile.Top__io_mem_${i}_aw_valid;
+      mem_aw_ready[$i] = &tile.Top__io_mem_${i}_aw_ready;
+      mem_aw_bits_addr[$i] = &tile.Top__io_mem_${i}_aw_bits_addr;
+      mem_aw_bits_id[$i] = &tile.Top__io_mem_${i}_aw_bits_id;
+      mem_aw_bits_size[$i] = &tile.Top__io_mem_${i}_aw_bits_size;
+      mem_aw_bits_len[$i] = &tile.Top__io_mem_${i}_aw_bits_len;
+
+      mem_w_valid[$i] = &tile.Top__io_mem_${i}_w_valid;
+      mem_w_ready[$i] = &tile.Top__io_mem_${i}_w_ready;
+      mem_w_bits_data[$i] = &tile.Top__io_mem_${i}_w_bits_data;
+      mem_w_bits_strb[$i] = &tile.Top__io_mem_${i}_w_bits_strb;
+      mem_w_bits_last[$i] = &tile.Top__io_mem_${i}_w_bits_last;
+
+      mem_b_valid[$i] = &tile.Top__io_mem_${i}_b_valid;
+      mem_b_ready[$i] = &tile.Top__io_mem_${i}_b_ready;
+      mem_b_bits_resp[$i] = &tile.Top__io_mem_${i}_b_bits_resp;
+      mem_b_bits_id[$i] = &tile.Top__io_mem_${i}_b_bits_id;
+
+      mem_r_valid[$i] = &tile.Top__io_mem_${i}_r_valid;
+      mem_r_ready[$i] = &tile.Top__io_mem_${i}_r_ready;
+      mem_r_bits_resp[$i] = &tile.Top__io_mem_${i}_r_bits_resp;
+      mem_r_bits_id[$i] = &tile.Top__io_mem_${i}_r_bits_id;
+      mem_r_bits_data[$i] = &tile.Top__io_mem_${i}_r_bits_data;
+      mem_r_bits_last[$i] = &tile.Top__io_mem_${i}_r_bits_last;
+
+    """ }.mkString
+
+    val f = createOutputFile(s"$topModuleName.$configClassName.tb.cpp")
+    f.write(assigns)
+    f.close
+  }
 }

src/main/scala/Testing.scala

@@ -152,7 +152,10 @@ object TestGenerator extends App with FileSystemUtilities {
   //Driver.elaborate(gen, configName = configClassName)
 
   TestGeneration.generateMakefrag(topModuleName, configClassName)
-  TestBenchGeneration.generateVerilogFragement(
+  TestBenchGeneration.generateVerilogFragment(
+    topModuleName, configClassName,
+    paramsFromConfig(NMemoryChannels))
+  TestBenchGeneration.generateCPPFragment(
     topModuleName, configClassName,
     paramsFromConfig(NMemoryChannels))