From bf19440db56867e56e25ce55a2ebf6a31b6b2528 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Sat, 26 Aug 2017 02:47:04 -0700
Subject: [PATCH 01/20] SystemBus: use a full buffer on slaves

---
 src/main/scala/coreplex/SystemBus.scala     | 2 +-
 src/main/scala/devices/tilelink/Error.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 30cd999c..b2558a2a 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -12,7 +12,7 @@ case class SystemBusParams(
   beatBytes: Int,
   blockBytes: Int,
   masterBuffering: BufferParams = BufferParams.default,
-  slaveBuffering: BufferParams = BufferParams.flow // TODO should be BufferParams.none on BCE
+  slaveBuffering: BufferParams = BufferParams.default
 ) extends TLBusParams
 
 case object SystemBusParams extends Field[SystemBusParams]
diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala
index bc43b4ff..d054922e 100644
--- a/src/main/scala/devices/tilelink/Error.scala
+++ b/src/main/scala/devices/tilelink/Error.scala
@@ -97,5 +97,5 @@ trait HasSystemErrorSlave extends HasSystemBus {
   private val params = p(ErrorParams)
   val error = LazyModule(new TLError(params, sbus.beatBytes))
 
-  error.node := TLBuffer(BufferParams.pipe)(sbus.toSlave)
+  error.node := sbus.toSlave
 }

From a62ce0afe630b40b5631a49e71ff75869738adc9 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Tue, 29 Aug 2017 10:36:46 -0700
Subject: [PATCH 02/20] TLBuffer: Add a nodedebugstring for quick browsing of
 the properties of the buffer.

---
 src/main/scala/diplomacy/Parameters.scala |  3 +++
 src/main/scala/tilelink/Buffer.scala      | 17 ++++++++++++++---
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/diplomacy/Parameters.scala b/src/main/scala/diplomacy/Parameters.scala
index a16f70aa..f7273e6a 100644
--- a/src/main/scala/diplomacy/Parameters.scala
+++ b/src/main/scala/diplomacy/Parameters.scala
@@ -279,6 +279,9 @@ case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
       sq.io.enq <> x
       sq.io.deq
     }
+
+  override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
+
 }
 
 object BufferParams
diff --git a/src/main/scala/tilelink/Buffer.scala b/src/main/scala/tilelink/Buffer.scala
index 9a741ab3..09b76b0a 100644
--- a/src/main/scala/tilelink/Buffer.scala
+++ b/src/main/scala/tilelink/Buffer.scala
@@ -8,6 +8,19 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
 
+class TLBufferNode (
+  a: BufferParams,
+  b: BufferParams,
+  c: BufferParams,
+  d: BufferParams,
+  e: BufferParams)(implicit p: Parameters) extends TLAdapterNode(
+    clientFn  = { p => p.copy(minLatency = p.minLatency + b.latency + c.latency) },
+    managerFn = { p => p.copy(minLatency = p.minLatency + a.latency + d.latency) }
+) {
+  override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
+
+}
+
 class TLBuffer(
   a: BufferParams,
   b: BufferParams,
@@ -19,9 +32,7 @@ class TLBuffer(
   def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
   def this()(implicit p: Parameters) = this(BufferParams.default)
 
-  val node = TLAdapterNode(
-    clientFn  = { p => p.copy(minLatency = p.minLatency + b.latency + c.latency) },
-    managerFn = { p => p.copy(minLatency = p.minLatency + a.latency + d.latency) })
+  val node = new TLBufferNode(a, b, c, d, e)
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {

From 656609d610e412006da9abdd301e9c48664f5f19 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 30 Aug 2017 13:28:11 -0700
Subject: [PATCH 03/20] SystemBus: split FIFOFixers along bus boundaries

If you have a system with a lot of periphery slaves, you wan to FIFO fix
them on the periphery bus rather than paying the circuit cost at the sbus.
---
 src/main/scala/coreplex/SystemBus.scala | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index b2558a2a..05fc6081 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -29,12 +29,14 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
   private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
+  private val pbus_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
   master_splitter.node :=* tile_fixer.node
   master_splitter.node :=* port_fixer.node
+  pbus_fixer.node :*= outwardWWNode
 
   def toSplitSlaves: TLOutwardNode = outwardSplitNode
 
-  val toPeripheryBus: TLOutwardNode = outwardWWNode
+  val toPeripheryBus: TLOutwardNode = pbus_fixer.node
 
   val toMemoryBus: TLOutwardNode = outwardNode
 

From f7330028ccbf17966fa0293cecb4c752f54a0d9a Mon Sep 17 00:00:00 2001
From: Henry Styles <hes@sifive.com>
Date: Fri, 25 Aug 2017 18:12:25 -0700
Subject: [PATCH 04/20] Add optional frontbus for peripherals mastering into
 SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2
 side of splitter

---
 src/main/scala/coreplex/FrontBus.scala | 60 ++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 src/main/scala/coreplex/FrontBus.scala

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
new file mode 100644
index 00000000..8a492c2d
--- /dev/null
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -0,0 +1,60 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.coreplex
+
+import Chisel._
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
+
+case class FrontBusParams(
+  beatBytes: Int,
+  blockBytes: Int,
+  masterBuffering: BufferParams = BufferParams.default,
+  slaveBuffering: BufferParams = BufferParams.none // TODO should be BufferParams.none on BCE
+) extends TLBusParams
+
+case object FrontBusParams extends Field[FrontBusParams]
+
+class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
+  xbar.suggestName("FrontBus")
+
+  def fromSyncMasters(params: BufferParams = BufferParams.default, buffers: Int = 1): TLInwardNode = {
+    val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
+    for(i<-1 until buffers) {
+      buf(i).node :=* buf(i-1).node
+    }
+    inwardNode :=* buf(buffers-1).node
+    if(buffers>0) buf(0).node else inwardNode
+  }
+
+  def fromSyncPorts(params: BufferParams =  BufferParams.default, buffers: Int = 1): TLInwardNode = {
+    val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
+    for(i<-1 until buffers) {
+      buf(i).node :=* buf(i-1).node
+    }
+    inwardNode :=* buf(buffers-1).node
+    if(buffers>0) buf(0).node else inwardNode
+  }
+
+  def fromSyncFIFOMaster(params: BufferParams =  BufferParams.default, buffers: Int = 1): TLInwardNode = fromSyncPorts(params, buffers)
+
+
+
+  def toSystemBus : TLOutwardNode = outwardBufNode
+
+}
+
+/** Provides buses that serve as attachment points,
+  * for use in traits that connect individual devices or external ports.
+  */
+trait HasFrontBus extends HasSystemBus {
+  private val frontbusParams = p(FrontBusParams)
+  val frontbusBeatBytes = frontbusParams.beatBytes
+
+  val frontbus = new FrontBus(frontbusParams)
+
+  sbus.fromSyncPorts() := frontbus.toSystemBus
+
+}

From d5b62dffda92cd1e701062e4247c8ef877b0e15d Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 30 Aug 2017 13:57:08 -0700
Subject: [PATCH 05/20] SystemBus: add stupidly many (4 more) buffers from
 sbus=>pbus

This should probably be reverted.
---
 src/main/scala/coreplex/SystemBus.scala | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 05fc6081..bbbc45ff 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -36,7 +36,15 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def toSplitSlaves: TLOutwardNode = outwardSplitNode
 
-  val toPeripheryBus: TLOutwardNode = pbus_fixer.node
+  private val pbusBuffer0 = LazyModule(new TLBuffer(BufferParams.default))
+  private val pbusBuffer1 = LazyModule(new TLBuffer(BufferParams.default))
+  private val pbusBuffer2 = LazyModule(new TLBuffer(BufferParams.default))
+  private val pbusBuffer3 = LazyModule(new TLBuffer(BufferParams.default))
+  pbusBuffer0.node :*= pbus_fixer.node
+  pbusBuffer1.node :*= pbusBuffer0.node
+  pbusBuffer2.node :*= pbusBuffer1.node
+  pbusBuffer3.node :*= pbusBuffer2.node
+  val toPeripheryBus: TLOutwardNode = pbusBuffer3.node
 
   val toMemoryBus: TLOutwardNode = outwardNode
 

From 183fefb2b9d424f7ab9085b53996bfc57a7743d5 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 15:27:56 -0700
Subject: [PATCH 06/20] Front/SystemBus: allow naming the intermediate TLNodes
 that get sprinkled in

---
 src/main/scala/coreplex/FrontBus.scala  | 20 +++++++-------------
 src/main/scala/coreplex/SystemBus.scala | 21 +++++++++++++--------
 2 files changed, 20 insertions(+), 21 deletions(-)

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 8a492c2d..ae791b4b 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -20,8 +20,12 @@ case object FrontBusParams extends Field[FrontBusParams]
 class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
   xbar.suggestName("FrontBus")
 
-  def fromSyncMasters(params: BufferParams = BufferParams.default, buffers: Int = 1): TLInwardNode = {
+  def fromSyncMasters(params: BufferParams = BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode =
+    fromSyncPorts(params, buffers, name)
+
+  def fromSyncPorts(params: BufferParams =  BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode = {
     val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
+    name.foreach { n => buf.zipWithIndex foreach {case (b, i) => b.suggestName(s"FrontBus_${n}_${i}_TLBuffer")}}
     for(i<-1 until buffers) {
       buf(i).node :=* buf(i-1).node
     }
@@ -29,18 +33,8 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrap
     if(buffers>0) buf(0).node else inwardNode
   }
 
-  def fromSyncPorts(params: BufferParams =  BufferParams.default, buffers: Int = 1): TLInwardNode = {
-    val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
-    for(i<-1 until buffers) {
-      buf(i).node :=* buf(i-1).node
-    }
-    inwardNode :=* buf(buffers-1).node
-    if(buffers>0) buf(0).node else inwardNode
-  }
-
-  def fromSyncFIFOMaster(params: BufferParams =  BufferParams.default, buffers: Int = 1): TLInwardNode = fromSyncPorts(params, buffers)
-
-
+  def fromSyncFIFOMaster(params: BufferParams =  BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode =
+    fromSyncPorts(params, buffers, name)
 
   def toSystemBus : TLOutwardNode = outwardBufNode
 
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index bbbc45ff..0d37bc0c 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -52,27 +52,30 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def fromCoherentChip: TLInwardNode = inwardNode
 
-  def fromSyncTiles(params: BufferParams): TLInwardNode = {
+  def fromSyncTiles(params: BufferParams, name: Option[String] = None): TLInwardNode = {
     val buf = LazyModule(new TLBuffer(params))
+    name.foreach{n => buf.suggestName(s"SystemBus_${n}_TLBuffer")}
     tile_fixer.node :=* buf.node
     buf.node
   }
 
-  def fromRationalTiles(dir: RationalDirection): TLRationalInwardNode = {
+  def fromRationalTiles(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
     val sink = LazyModule(new TLRationalCrossingSink(direction = dir))
+    name.foreach{n => sink.suggestName(s"SystemBus_${n}_TLRationalCrossingSink")}
     tile_fixer.node :=* sink.node
     sink.node
   }
 
-  def fromAsyncTiles(depth: Int, sync: Int): TLAsyncInwardNode = {
+  def fromAsyncTiles(depth: Int, sync: Int, name: Option[String] = None): TLAsyncInwardNode = {
     val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
+    name.foreach{n => sink.suggestName(s"SystemBus_${n}_TLAsyncCrossingSink")}
     tile_fixer.node :=* sink.node
     sink.node
   }
 
   def fromSyncPorts(params: BufferParams =  BufferParams.default, name: Option[String] = None): TLInwardNode = {
     val buffer = LazyModule(new TLBuffer(params))
-    name.foreach{ n => buffer.suggestName(s"${n}_TLBuffer") }
+    name.foreach{ n => buffer.suggestName(s"SystemBus_${n}_TLBuffer") }
     port_fixer.node :=* buffer.node
     buffer.node
   }
@@ -81,21 +84,23 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
     fromSyncPorts(params, name)
   }
 
-  def fromAsyncPorts(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = {
+  def fromAsyncPorts(depth: Int = 8, sync: Int = 3, name : Option[String] = None): TLAsyncInwardNode = {
     val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
+    name.foreach{ n => sink.suggestName(s"SystemBus_${n}_TLAsyncCrossingSink") }
     port_fixer.node :=* sink.node
     sink.node
   }
 
-  def fromAsyncFIFOMaster(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = fromAsyncPorts(depth, sync)
+  def fromAsyncFIFOMaster(depth: Int = 8, sync: Int = 3, name: Option[String] = None): TLAsyncInwardNode = fromAsyncPorts(depth, sync, name)
 
-  def fromRationalPorts(dir: RationalDirection): TLRationalInwardNode = {
+  def fromRationalPorts(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
     val sink = LazyModule(new TLRationalCrossingSink(dir))
+    name.foreach{ n => sink.suggestName(s"SystemBus_${n}_TLRationalCrossingSink") }
     port_fixer.node :=* sink.node
     sink.node
   }
 
-  def fromRationalFIFOMaster(dir: RationalDirection): TLRationalInwardNode = fromRationalPorts(dir)
+  def fromRationalFIFOMaster(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = fromRationalPorts(dir, name)
 }
 
 /** Provides buses that serve as attachment points,

From 32cb358c81d9cf32e67b3cf21cd400cf71141e7d Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Wed, 30 Aug 2017 15:23:10 -0700
Subject: [PATCH 07/20] coreplex: include optional tile name for downstream
 name stabilization

---
 src/main/scala/coreplex/RocketCoreplex.scala | 6 +++---
 src/main/scala/tile/RocketTile.scala         | 3 ++-
 src/main/scala/tilelink/Bus.scala            | 6 ++++--
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala
index a30cdad5..11d64887 100644
--- a/src/main/scala/coreplex/RocketCoreplex.scala
+++ b/src/main/scala/coreplex/RocketCoreplex.scala
@@ -52,17 +52,17 @@ trait HasRocketTiles extends HasSystemBus
       case AsynchronousCrossing(depth, sync) => {
         val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
         sbus.fromAsyncTiles(depth, sync) :=* wrapper.masterNode
-        wrapper.slaveNode :*= pbus.toAsyncSlaves(sync)
+        wrapper.slaveNode :*= pbus.toAsyncSlaves(sync)(c.name)
         wrapper
       }
       case RationalCrossing(direction) => {
         val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
         sbus.fromRationalTiles(direction) :=* wrapper.masterNode
-        wrapper.slaveNode :*= pbus.toRationalSlaves
+        wrapper.slaveNode :*= pbus.toRationalSlaves(c.name)
         wrapper
       }
     }
-    wrapper.suggestName("tile") // Try to stabilize this name for downstream tools
+    c.name.foreach(wrapper.suggestName) // Try to stabilize this name for downstream tools
 
     // Local Interrupts must be synchronized to the core clock
     // before being passed into this module.
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index 3490b6c9..88541bff 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -18,7 +18,8 @@ case class RocketTileParams(
     rocc: Seq[RoCCParams] = Nil,
     btb: Option[BTBParams] = Some(BTBParams()),
     dataScratchpadBytes: Int = 0,
-    boundaryBuffers: Boolean = false) extends TileParams {
+    boundaryBuffers: Boolean = false,
+    name: Option[String] = Some("tile")) extends TileParams {
   require(icache.isDefined)
   require(dcache.isDefined)
 }
diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index 9d72ad7c..612b8cdd 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -63,14 +63,16 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
 
   def bufferToSlaves: TLOutwardNode = outwardBufNode 
 
-  def toAsyncSlaves(sync: Int = 3): TLAsyncOutwardNode = {
+  def toAsyncSlaves(sync: Int = 3)(name: Option[String] = None): TLAsyncOutwardNode = {
     val source = LazyModule(new TLAsyncCrossingSource(sync))
+    name.foreach(source.suggestName)
     source.node :*= outwardNode
     source.node
   }
 
-  def toRationalSlaves: TLRationalOutwardNode = {
+  def toRationalSlaves(name: Option[String] = None): TLRationalOutwardNode = {
     val source = LazyModule(new TLRationalCrossingSource())
+    name.foreach(source.suggestName)
     source.node :*= outwardNode
     source.node
   }

From c99afe4c6649063ee541db65c78e61c5065a1ea7 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 16:21:08 -0700
Subject: [PATCH 08/20] buses: Name all the things.

---
 src/main/scala/coreplex/FrontBus.scala       |  5 ++--
 src/main/scala/coreplex/MemoryBus.scala      |  3 +--
 src/main/scala/coreplex/PeripheryBus.scala   |  3 +--
 src/main/scala/coreplex/RocketCoreplex.scala |  2 +-
 src/main/scala/coreplex/SystemBus.scala      | 20 +++++++++------
 src/main/scala/tilelink/Bus.scala            | 27 ++++++++++++++------
 6 files changed, 36 insertions(+), 24 deletions(-)

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index ae791b4b..69453b47 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -17,15 +17,14 @@ case class FrontBusParams(
 
 case object FrontBusParams extends Field[FrontBusParams]
 
-class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
-  xbar.suggestName("FrontBus")
+class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") {
 
   def fromSyncMasters(params: BufferParams = BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode =
     fromSyncPorts(params, buffers, name)
 
   def fromSyncPorts(params: BufferParams =  BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode = {
     val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
-    name.foreach { n => buf.zipWithIndex foreach {case (b, i) => b.suggestName(s"FrontBus_${n}_${i}_TLBuffer")}}
+    name.foreach { n => buf.zipWithIndex foreach {case (b, i) => b.suggestName(s"${busName}_${n}_${i}_TLBuffer")}}
     for(i<-1 until buffers) {
       buf(i).node :=* buf(i-1).node
     }
diff --git a/src/main/scala/coreplex/MemoryBus.scala b/src/main/scala/coreplex/MemoryBus.scala
index d71507ba..1e2fffdd 100644
--- a/src/main/scala/coreplex/MemoryBus.scala
+++ b/src/main/scala/coreplex/MemoryBus.scala
@@ -43,8 +43,7 @@ case class MemoryBusParams(
 case object MemoryBusParams extends Field[MemoryBusParams]
 
 /** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
-class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params)(p) {
-  xbar.suggestName("MemoryBus")
+class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "MemoryBus")(p) {
 
   def fromCoherenceManager: TLInwardNode = inwardBufNode
   def toDRAMController: TLOutwardNode = outwardBufNode
diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala
index 02d098c2..b51df08a 100644
--- a/src/main/scala/coreplex/PeripheryBus.scala
+++ b/src/main/scala/coreplex/PeripheryBus.scala
@@ -21,8 +21,7 @@ case class PeripheryBusParams(
 
 case object PeripheryBusParams extends Field[PeripheryBusParams]
 
-class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
-  xbar.suggestName("PeripheryBus")
+class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") {
 
   def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
     TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)
diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala
index 11d64887..9137bd29 100644
--- a/src/main/scala/coreplex/RocketCoreplex.scala
+++ b/src/main/scala/coreplex/RocketCoreplex.scala
@@ -52,7 +52,7 @@ trait HasRocketTiles extends HasSystemBus
       case AsynchronousCrossing(depth, sync) => {
         val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
         sbus.fromAsyncTiles(depth, sync) :=* wrapper.masterNode
-        wrapper.slaveNode :*= pbus.toAsyncSlaves(sync)(c.name)
+        wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, c.name)
         wrapper
       }
       case RationalCrossing(direction) => {
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 0d37bc0c..df648704 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -17,10 +17,10 @@ case class SystemBusParams(
 
 case object SystemBusParams extends Field[SystemBusParams]
 
-class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
-  xbar.suggestName("SystemBus")
+class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "SystemBus") {
 
   private val master_splitter = LazyModule(new TLSplitter)  // Allows cycle-free connection to external networks
+  master_splitter.suggestName(s"${busName}_master_TLSplitter"}
   inwardNode :=* master_splitter.node
   def busView = master_splitter.node.edgesIn.head
 
@@ -28,8 +28,12 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   protected def outwardSplitNode: TLOutwardNode = master_splitter.node
 
   private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
+  tile_fixer.suggestName(s"${busName}_tile_TLFIFOFixer")
   private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
+  port_fixer.suggestName(s"${busName}_port_TLFIFOFixer")
   private val pbus_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
+  pbus_fixer.suggestName(s"${busName}_pbus_TLFIFOFixer")
+  
   master_splitter.node :=* tile_fixer.node
   master_splitter.node :=* port_fixer.node
   pbus_fixer.node :*= outwardWWNode
@@ -54,28 +58,28 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def fromSyncTiles(params: BufferParams, name: Option[String] = None): TLInwardNode = {
     val buf = LazyModule(new TLBuffer(params))
-    name.foreach{n => buf.suggestName(s"SystemBus_${n}_TLBuffer")}
+    name.foreach{n => buf.suggestName(s"${busName}_${n}_TLBuffer")}
     tile_fixer.node :=* buf.node
     buf.node
   }
 
   def fromRationalTiles(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
     val sink = LazyModule(new TLRationalCrossingSink(direction = dir))
-    name.foreach{n => sink.suggestName(s"SystemBus_${n}_TLRationalCrossingSink")}
+    name.foreach{n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink")}
     tile_fixer.node :=* sink.node
     sink.node
   }
 
   def fromAsyncTiles(depth: Int, sync: Int, name: Option[String] = None): TLAsyncInwardNode = {
     val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
-    name.foreach{n => sink.suggestName(s"SystemBus_${n}_TLAsyncCrossingSink")}
+    name.foreach{n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossignSink")}
     tile_fixer.node :=* sink.node
     sink.node
   }
 
   def fromSyncPorts(params: BufferParams =  BufferParams.default, name: Option[String] = None): TLInwardNode = {
     val buffer = LazyModule(new TLBuffer(params))
-    name.foreach{ n => buffer.suggestName(s"SystemBus_${n}_TLBuffer") }
+    name.foreach{ n => buffer.suggestName(s"${busName}_${n}_TLBuffer") }
     port_fixer.node :=* buffer.node
     buffer.node
   }
@@ -86,7 +90,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def fromAsyncPorts(depth: Int = 8, sync: Int = 3, name : Option[String] = None): TLAsyncInwardNode = {
     val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
-    name.foreach{ n => sink.suggestName(s"SystemBus_${n}_TLAsyncCrossingSink") }
+    name.foreach{ n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
     port_fixer.node :=* sink.node
     sink.node
   }
@@ -95,7 +99,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def fromRationalPorts(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
     val sink = LazyModule(new TLRationalCrossingSink(dir))
-    name.foreach{ n => sink.suggestName(s"SystemBus_${n}_TLRationalCrossingSink") }
+    name.foreach{ n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
     port_fixer.node :=* sink.node
     sink.node
   }
diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index 612b8cdd..2906b52b 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -21,7 +21,8 @@ trait TLBusParams {
   def blockOffset: Int = log2Up(blockBytes)
 }
 
-abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends TLBusParams {
+abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters) extends TLBusParams {
+
   val beatBytes = params.beatBytes
   val blockBytes = params.blockBytes
   val masterBuffering = params.masterBuffering
@@ -30,10 +31,16 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
   private val delayProb = p(TLBusDelayProbability)
 
   protected val xbar = LazyModule(new TLXbar)
+  xbar.suggestName(busName)
   private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
+  master_buffer.suggestName(s"${busName}_master_TLBuffer")
   private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
+  slave_buffer.suggestName(s"${busName}_slave_TLBuffer")
   private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
+  slave_frag.suggestName(s"${busName}_slave_TLFragmenter")
+  
   private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
+  slave_ww.suggestName(s"${busName}_slave_TLWidthWidget")
 
   private val delayedNode = if (delayProb > 0.0) {
     val firstDelay = LazyModule(new TLDelayer(delayProb))
@@ -63,44 +70,48 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
 
   def bufferToSlaves: TLOutwardNode = outwardBufNode 
 
-  def toAsyncSlaves(sync: Int = 3)(name: Option[String] = None): TLAsyncOutwardNode = {
+  def toAsyncSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
     val source = LazyModule(new TLAsyncCrossingSource(sync))
-    name.foreach(source.suggestName)
+    name.foreach{ n => source.suggestName(s"${busName}_${n}_TLAsyncCrossingSource")}
     source.node :*= outwardNode
     source.node
   }
 
   def toRationalSlaves(name: Option[String] = None): TLRationalOutwardNode = {
     val source = LazyModule(new TLRationalCrossingSource())
-    name.foreach(source.suggestName)
+    name.foreach{ n => source.suggestName(s"${busName}_${n}_TLRationalCrossingSource")}
     source.node :*= outwardNode
     source.node
   }
 
   def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
 
-  def toAsyncVariableWidthSlaves(sync: Int = 3): TLAsyncOutwardNode = {
+  def toAsyncVariableWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
     val source = LazyModule(new TLAsyncCrossingSource(sync))
+    name.foreach {n =>  source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
     source.node :*= outwardFragNode
     source.node
   }
 
-  def toRationalVariableWidthSlaves: TLRationalOutwardNode = {
+  def toRationalVariableWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
     val source = LazyModule(new TLRationalCrossingSource())
+    name.foreach {n =>  source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
     source.node :*= outwardFragNode
     source.node
   }
 
   def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
 
-  def toAsyncFixedWidthSlaves(sync: Int = 3): TLAsyncOutwardNode = {
+  def toAsyncFixedWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
     val source = LazyModule(new TLAsyncCrossingSource(sync))
+    name.foreach { n => source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
     source.node := outwardWWNode
     source.node
   }
 
-  def toRationalFixedWidthSlaves: TLRationalOutwardNode = {
+  def toRationalFixedWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
     val source = LazyModule(new TLRationalCrossingSource())
+    name.foreach {n => source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
     source.node :*= outwardWWNode
     source.node
   }

From 57d0360c35931be0234f6795ec8e5dd897479cc8 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 17:51:30 -0700
Subject: [PATCH 09/20] frontbus: Name the connection.

---
 src/main/scala/coreplex/FrontBus.scala  | 2 +-
 src/main/scala/coreplex/SystemBus.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 69453b47..3b3aca9d 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -48,6 +48,6 @@ trait HasFrontBus extends HasSystemBus {
 
   val frontbus = new FrontBus(frontbusParams)
 
-  sbus.fromSyncPorts() := frontbus.toSystemBus
+  sbus.fromSyncPorts(name = Some("FrontBus")) := frontbus.toSystemBus
 
 }
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index df648704..1c9849aa 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -20,7 +20,7 @@ case object SystemBusParams extends Field[SystemBusParams]
 class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "SystemBus") {
 
   private val master_splitter = LazyModule(new TLSplitter)  // Allows cycle-free connection to external networks
-  master_splitter.suggestName(s"${busName}_master_TLSplitter"}
+  master_splitter.suggestName(s"${busName}_master_TLSplitter"})
   inwardNode :=* master_splitter.node
   def busView = master_splitter.node.edgesIn.head
 

From 3bde9506c6903eb699dec3c7861e5b4104cce1e2 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Wed, 30 Aug 2017 17:57:52 -0700
Subject: [PATCH 10/20] coreplex: allow buffer chains on certain bus ports

---
 src/main/scala/coreplex/FrontBus.scala       | 10 +--
 src/main/scala/coreplex/MemoryBus.scala      |  1 -
 src/main/scala/coreplex/PeripheryBus.scala   |  2 +-
 src/main/scala/coreplex/RocketCoreplex.scala | 26 +++----
 src/main/scala/coreplex/SystemBus.scala      | 71 +++++++++++---------
 src/main/scala/tile/RocketTile.scala         |  3 +-
 src/main/scala/tilelink/Bus.scala            | 14 ++++
 7 files changed, 74 insertions(+), 53 deletions(-)

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 3b3aca9d..47de22b0 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -23,13 +23,9 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrap
     fromSyncPorts(params, buffers, name)
 
   def fromSyncPorts(params: BufferParams =  BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode = {
-    val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
-    name.foreach { n => buf.zipWithIndex foreach {case (b, i) => b.suggestName(s"${busName}_${n}_${i}_TLBuffer")}}
-    for(i<-1 until buffers) {
-      buf(i).node :=* buf(i-1).node
-    }
-    inwardNode :=* buf(buffers-1).node
-    if(buffers>0) buf(0).node else inwardNode
+    val (in, out) = bufferChain(buffers, params, name)
+    inwardNode :=* out
+    in
   }
 
   def fromSyncFIFOMaster(params: BufferParams =  BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode =
diff --git a/src/main/scala/coreplex/MemoryBus.scala b/src/main/scala/coreplex/MemoryBus.scala
index 1e2fffdd..277b54c3 100644
--- a/src/main/scala/coreplex/MemoryBus.scala
+++ b/src/main/scala/coreplex/MemoryBus.scala
@@ -44,7 +44,6 @@ case object MemoryBusParams extends Field[MemoryBusParams]
 
 /** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
 class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "MemoryBus")(p) {
-
   def fromCoherenceManager: TLInwardNode = inwardBufNode
   def toDRAMController: TLOutwardNode = outwardBufNode
   def toVariableWidthSlave: TLOutwardNode = outwardFragNode
diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala
index b51df08a..22eab1b2 100644
--- a/src/main/scala/coreplex/PeripheryBus.scala
+++ b/src/main/scala/coreplex/PeripheryBus.scala
@@ -48,5 +48,5 @@ trait HasPeripheryBus extends HasSystemBus {
   val pbus = new PeripheryBus(pbusParams)
 
   // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
-  pbus.fromSystemBus := sbus.toPeripheryBus
+  pbus.fromSystemBus := sbus.toPeripheryBus(nBuffers = 4)
 }
diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala
index 9137bd29..d1e7fd0c 100644
--- a/src/main/scala/coreplex/RocketCoreplex.scala
+++ b/src/main/scala/coreplex/RocketCoreplex.scala
@@ -35,34 +35,34 @@ trait HasRocketTiles extends HasSystemBus
   // Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
   // according to the specified type of clock crossing.
   val wiringTuple = localIntNodes.zip(tileParams).zipWithIndex
-  val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case ((lip, c), i) =>
+  val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case ((lip, tp), i) =>
     val pWithExtra = p.alterPartial {
-      case TileKey => c
-      case BuildRoCC => c.rocc
+      case TileKey => tp
+      case BuildRoCC => tp.rocc
       case SharedMemoryTLEdge => sharedMemoryTLEdge
     }
 
     val wrapper = crossing match {
       case SynchronousCrossing(params) => {
-        val wrapper = LazyModule(new SyncRocketTile(c, i)(pWithExtra))
-        sbus.fromSyncTiles(params) :=* wrapper.masterNode 
+        val wrapper = LazyModule(new SyncRocketTile(tp, i)(pWithExtra))
+        sbus.fromSyncTiles(params, tp.externalBuffers, tp.name) :=* wrapper.masterNode
         wrapper.slaveNode :*= pbus.bufferToSlaves
         wrapper
       }
       case AsynchronousCrossing(depth, sync) => {
-        val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
-        sbus.fromAsyncTiles(depth, sync) :=* wrapper.masterNode
-        wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, c.name)
+        val wrapper = LazyModule(new AsyncRocketTile(tp, i)(pWithExtra))
+        sbus.fromAsyncTiles(depth, sync, tp.externalBuffers, tp.name) :=* wrapper.masterNode
+        wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, tp.name)
         wrapper
       }
       case RationalCrossing(direction) => {
-        val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
-        sbus.fromRationalTiles(direction) :=* wrapper.masterNode
-        wrapper.slaveNode :*= pbus.toRationalSlaves(c.name)
+        val wrapper = LazyModule(new RationalRocketTile(tp, i)(pWithExtra))
+        sbus.fromRationalTiles(direction, tp.externalBuffers, tp.name) :=* wrapper.masterNode
+        wrapper.slaveNode :*= pbus.toRationalSlaves(tp.name)
         wrapper
       }
     }
-    c.name.foreach(wrapper.suggestName) // Try to stabilize this name for downstream tools
+    tp.name.foreach(wrapper.suggestName) // Try to stabilize this name for downstream tools
 
     // Local Interrupts must be synchronized to the core clock
     // before being passed into this module.
@@ -77,7 +77,7 @@ trait HasRocketTiles extends HasSystemBus
     val periphIntXbar = LazyModule(new IntXbar)
     periphIntXbar.intnode := clint.intnode                  // msip+mtip
     periphIntXbar.intnode := plic.intnode                   // meip
-    if (c.core.useVM) periphIntXbar.intnode := plic.intnode // seip
+    if (tp.core.useVM) periphIntXbar.intnode := plic.intnode // seip
     wrapper.periphIntNode := periphIntXbar.intnode
 
     val coreIntXbar = LazyModule(new IntXbar)
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 1c9849aa..f1e16512 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -20,35 +20,28 @@ case object SystemBusParams extends Field[SystemBusParams]
 class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "SystemBus") {
 
   private val master_splitter = LazyModule(new TLSplitter)  // Allows cycle-free connection to external networks
-  master_splitter.suggestName(s"${busName}_master_TLSplitter"})
+  master_splitter.suggestName(s"${busName}_master_TLSplitter")
   inwardNode :=* master_splitter.node
   def busView = master_splitter.node.edgesIn.head
 
   protected def inwardSplitNode: TLInwardNode = master_splitter.node
   protected def outwardSplitNode: TLOutwardNode = master_splitter.node
 
-  private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
-  tile_fixer.suggestName(s"${busName}_tile_TLFIFOFixer")
   private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
   port_fixer.suggestName(s"${busName}_port_TLFIFOFixer")
+  master_splitter.node :=* port_fixer.node
+
   private val pbus_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
   pbus_fixer.suggestName(s"${busName}_pbus_TLFIFOFixer")
-  
-  master_splitter.node :=* tile_fixer.node
-  master_splitter.node :=* port_fixer.node
   pbus_fixer.node :*= outwardWWNode
 
   def toSplitSlaves: TLOutwardNode = outwardSplitNode
 
-  private val pbusBuffer0 = LazyModule(new TLBuffer(BufferParams.default))
-  private val pbusBuffer1 = LazyModule(new TLBuffer(BufferParams.default))
-  private val pbusBuffer2 = LazyModule(new TLBuffer(BufferParams.default))
-  private val pbusBuffer3 = LazyModule(new TLBuffer(BufferParams.default))
-  pbusBuffer0.node :*= pbus_fixer.node
-  pbusBuffer1.node :*= pbusBuffer0.node
-  pbusBuffer2.node :*= pbusBuffer1.node
-  pbusBuffer3.node :*= pbusBuffer2.node
-  val toPeripheryBus: TLOutwardNode = pbusBuffer3.node
+  def toPeripheryBus(nBuffers: Int): TLOutwardNode = {
+    val (in, out) = bufferChain(nBuffers, name = Some("PeripheryBus"))
+    in := pbus_fixer.node
+    out
+  }
 
   val toMemoryBus: TLOutwardNode = outwardNode
 
@@ -56,25 +49,43 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def fromCoherentChip: TLInwardNode = inwardNode
 
-  def fromSyncTiles(params: BufferParams, name: Option[String] = None): TLInwardNode = {
-    val buf = LazyModule(new TLBuffer(params))
-    name.foreach{n => buf.suggestName(s"${busName}_${n}_TLBuffer")}
-    tile_fixer.node :=* buf.node
-    buf.node
+  def fromSyncTiles(params: BufferParams, addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
+    val tile_buf = LazyModule(new TLBuffer(params))
+    name.foreach { n => tile_buf.suggestName(s"${busName}_${n}_TLBuffer") }
+    val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
+    name.foreach { n => tile_fixer.suggestName(s"${busName}_${n}_TLFIFOFixer") }
+    val (in, out) = bufferChain(addBuffers, name = name)
+
+    master_splitter.node :=* out
+    in :=* tile_fixer.node
+    tile_fixer.node :=* tile_buf.node
+    tile_buf.node
   }
 
-  def fromRationalTiles(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
-    val sink = LazyModule(new TLRationalCrossingSink(direction = dir))
-    name.foreach{n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink")}
-    tile_fixer.node :=* sink.node
-    sink.node
+  def fromRationalTiles(dir: RationalDirection, addBuffers: Int = 0, name: Option[String] = None): TLRationalInwardNode = {
+    val tile_sink = LazyModule(new TLRationalCrossingSink(direction = dir))
+    name.foreach{ n => tile_sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
+    val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
+    name.foreach { n => tile_fixer.suggestName(s"${busName}_${n}_TLFIFOFixer") }
+    val (in, out) = bufferChain(addBuffers, name = name)
+
+    master_splitter.node :=* out
+    in :=* tile_fixer.node
+    tile_fixer.node :=* tile_sink.node
+    tile_sink.node
   }
 
-  def fromAsyncTiles(depth: Int, sync: Int, name: Option[String] = None): TLAsyncInwardNode = {
-    val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
-    name.foreach{n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossignSink")}
-    tile_fixer.node :=* sink.node
-    sink.node
+  def fromAsyncTiles(depth: Int, sync: Int, addBuffers: Int = 0, name: Option[String] = None): TLAsyncInwardNode = {
+    val tile_sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
+    name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
+    val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
+    name.foreach { n => tile_fixer.suggestName(s"${busName}_${n}_TLFIFOFixer") }
+    val (in, out) = bufferChain(addBuffers, name = name)
+
+    master_splitter.node :=* out
+    in :=* tile_fixer.node
+    tile_fixer.node :=* tile_sink.node
+    tile_sink.node
   }
 
   def fromSyncPorts(params: BufferParams =  BufferParams.default, name: Option[String] = None): TLInwardNode = {
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index 88541bff..4b2ff7ca 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -19,7 +19,8 @@ case class RocketTileParams(
     btb: Option[BTBParams] = Some(BTBParams()),
     dataScratchpadBytes: Int = 0,
     boundaryBuffers: Boolean = false,
-    name: Option[String] = Some("tile")) extends TileParams {
+    name: Option[String] = Some("tile"),
+    externalBuffers: Int = 0) extends TileParams {
   require(icache.isDefined)
   require(dcache.isDefined)
 }
diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index 2906b52b..081906db 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -32,6 +32,7 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
 
   protected val xbar = LazyModule(new TLXbar)
   xbar.suggestName(busName)
+
   private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
   master_buffer.suggestName(s"${busName}_master_TLBuffer")
   private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
@@ -66,6 +67,19 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
   protected def inwardNode: TLInwardNode = xbar.node
   protected def inwardBufNode: TLInwardNode = master_buffer.node
 
+  protected def bufferChain(n: Int, params: BufferParams = BufferParams.default, name: Option[String] = None): (TLInwardNode, TLOutwardNode) = {
+    if (n > 0) {
+      val chain = List.fill(n)(LazyModule(new TLBuffer(params)))
+      name.foreach { n => chain.zipWithIndex foreach { case(b, i) => b.suggestName(s"${busName}_${n}_${i}_TLBuffer") } }
+      (chain.init zip chain.tail) foreach { case(prev, next) => next.node :=* prev.node }
+      (chain.head.node, chain.last.node)
+    } else {
+      val dummy = LazyModule(new TLBuffer(BufferParams.none))
+      dummy.suggestName(s"${busName}_${n}_empty_TLBuffer")
+      (dummy.node, dummy.node)
+    }
+  }
+
   def bufferFromMasters: TLInwardNode = inwardBufNode
 
   def bufferToSlaves: TLOutwardNode = outwardBufNode 

From c353f68dc0cd11a86f3502b16982195ec554fdb1 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 18:30:22 -0700
Subject: [PATCH 11/20] buses: name dummy buffers too

---
 src/main/scala/tilelink/Bus.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index 081906db..98b07003 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -67,15 +67,15 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
   protected def inwardNode: TLInwardNode = xbar.node
   protected def inwardBufNode: TLInwardNode = master_buffer.node
 
-  protected def bufferChain(n: Int, params: BufferParams = BufferParams.default, name: Option[String] = None): (TLInwardNode, TLOutwardNode) = {
-    if (n > 0) {
-      val chain = List.fill(n)(LazyModule(new TLBuffer(params)))
+  protected def bufferChain(depth: Int, params: BufferParams = BufferParams.default, name: Option[String] = None): (TLInwardNode, TLOutwardNode) = {
+    if (depth > 0) {
+      val chain = List.fill(depth)(LazyModule(new TLBuffer(params)))
       name.foreach { n => chain.zipWithIndex foreach { case(b, i) => b.suggestName(s"${busName}_${n}_${i}_TLBuffer") } }
       (chain.init zip chain.tail) foreach { case(prev, next) => next.node :=* prev.node }
       (chain.head.node, chain.last.node)
     } else {
       val dummy = LazyModule(new TLBuffer(BufferParams.none))
-      dummy.suggestName(s"${busName}_${n}_empty_TLBuffer")
+      name.foreach { n => dummy.suggestName(s"${busName}_${n}_empty_TLBuffer")}
       (dummy.node, dummy.node)
     }
   }

From 94f06dc85c60cac6b15e4bf25d4ffdf8bc61cbca Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 30 Aug 2017 19:23:18 -0700
Subject: [PATCH 12/20] pbus: turn down overkill buffering between PBus and
 SBus

---
 src/main/scala/coreplex/PeripheryBus.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala
index 22eab1b2..7e51691e 100644
--- a/src/main/scala/coreplex/PeripheryBus.scala
+++ b/src/main/scala/coreplex/PeripheryBus.scala
@@ -48,5 +48,5 @@ trait HasPeripheryBus extends HasSystemBus {
   val pbus = new PeripheryBus(pbusParams)
 
   // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
-  pbus.fromSystemBus := sbus.toPeripheryBus(nBuffers = 4)
+  pbus.fromSystemBus := sbus.toPeripheryBus(nBuffers = 1)
 }

From 667d966410d102bed5f8c6c13af2904bc00701aa Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 31 Aug 2017 13:00:37 -0700
Subject: [PATCH 13/20] TLBuffer: Create a wrapper module for TLBufferChain, to
 allow for more stable naming

---
 src/main/scala/coreplex/FrontBus.scala  |  3 ++-
 src/main/scala/coreplex/SystemBus.scala |  2 +-
 src/main/scala/tilelink/Buffer.scala    | 25 +++++++++++++++++++++++++
 src/main/scala/tilelink/Bus.scala       | 15 ++++-----------
 4 files changed, 32 insertions(+), 13 deletions(-)

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 47de22b0..79634165 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -23,7 +23,8 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrap
     fromSyncPorts(params, buffers, name)
 
   def fromSyncPorts(params: BufferParams =  BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode = {
-    val (in, out) = bufferChain(buffers, params, name)
+    require(params == BufferParams.default, "Only BufferParams.default supported for FrontBus at this time.")
+    val (in, out) = bufferChain(buffers, name)
     inwardNode :=* out
     in
   }
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index f1e16512..f3022731 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -38,7 +38,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   def toSplitSlaves: TLOutwardNode = outwardSplitNode
 
   def toPeripheryBus(nBuffers: Int): TLOutwardNode = {
-    val (in, out) = bufferChain(nBuffers, name = Some("PeripheryBus"))
+    val (in, out) = bufferChain(nBuffers, name = Some("pbus"))
     in := pbus_fixer.node
     out
   }
diff --git a/src/main/scala/tilelink/Buffer.scala b/src/main/scala/tilelink/Buffer.scala
index 09b76b0a..3a8869de 100644
--- a/src/main/scala/tilelink/Buffer.scala
+++ b/src/main/scala/tilelink/Buffer.scala
@@ -77,3 +77,28 @@ object TLBuffer
     buffer.node
   }
 }
+
+class TLBufferChain(depth: Int)(implicit p: Parameters) extends LazyModule {
+
+  val nodeIn = TLInputNode()
+  val nodeOut = TLOutputNode()
+
+  val buf_chain = if (depth > 0) {
+    val chain = List.fill(depth)(LazyModule(new TLBuffer(BufferParams.default)))
+
+    (chain.init zip chain.tail) foreach { case(prev, next) => next.node :=* prev.node }
+    chain
+  } else {
+    List(LazyModule(new TLBuffer(BufferParams.none)))
+  }
+
+  buf_chain.head.node :=* nodeIn
+  nodeOut :=* buf_chain.last.node
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in  = nodeIn.bundleIn
+      val out = nodeOut.bundleOut
+    }
+  }
+}
diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index 98b07003..d9a7f364 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -67,17 +67,10 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
   protected def inwardNode: TLInwardNode = xbar.node
   protected def inwardBufNode: TLInwardNode = master_buffer.node
 
-  protected def bufferChain(depth: Int, params: BufferParams = BufferParams.default, name: Option[String] = None): (TLInwardNode, TLOutwardNode) = {
-    if (depth > 0) {
-      val chain = List.fill(depth)(LazyModule(new TLBuffer(params)))
-      name.foreach { n => chain.zipWithIndex foreach { case(b, i) => b.suggestName(s"${busName}_${n}_${i}_TLBuffer") } }
-      (chain.init zip chain.tail) foreach { case(prev, next) => next.node :=* prev.node }
-      (chain.head.node, chain.last.node)
-    } else {
-      val dummy = LazyModule(new TLBuffer(BufferParams.none))
-      name.foreach { n => dummy.suggestName(s"${busName}_${n}_empty_TLBuffer")}
-      (dummy.node, dummy.node)
-    }
+  protected def bufferChain(depth: Int, name: Option[String] = None): (TLInwardNode, TLOutwardNode) = {
+    val chain = LazyModule(new TLBufferChain(depth))
+    name.foreach { n => chain.suggestName(s"${busName}_${n}_TLBufferChain")}
+    (chain.nodeIn, chain.nodeOut)
   }
 
   def bufferFromMasters: TLInwardNode = inwardBufNode

From 8fc4d78c84b598bd02d67bd21f7362390580dc16 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Fri, 1 Sep 2017 14:26:55 -0700
Subject: [PATCH 14/20] frontbus: provide fifofixer on the side of the front
 bus where masters connect

---
 src/main/scala/coreplex/FrontBus.scala | 33 +++++++++++++++++---------
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 79634165..3fd080d9 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -12,25 +12,36 @@ case class FrontBusParams(
   beatBytes: Int,
   blockBytes: Int,
   masterBuffering: BufferParams = BufferParams.default,
-  slaveBuffering: BufferParams = BufferParams.none // TODO should be BufferParams.none on BCE
+  slaveBuffering: BufferParams = BufferParams.none
 ) extends TLBusParams
 
 case object FrontBusParams extends Field[FrontBusParams]
 
 class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") {
 
-  def fromSyncMasters(params: BufferParams = BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode =
-    fromSyncPorts(params, buffers, name)
+  private val master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
+  master_fixer.suggestName(s"${busName}_master_TLFIFOFixer")
+  inwardBufNode :=* master_fixer.node
 
-  def fromSyncPorts(params: BufferParams =  BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode = {
-    require(params == BufferParams.default, "Only BufferParams.default supported for FrontBus at this time.")
-    val (in, out) = bufferChain(buffers, name)
-    inwardNode :=* out
+  def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
+    val (in, out) = bufferChain(addBuffers, name)
+    inwardBufNode :=* out
     in
   }
 
-  def fromSyncFIFOMaster(params: BufferParams =  BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode =
-    fromSyncPorts(params, buffers, name)
+  def fromSyncPorts(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
+    val (in, out) = bufferChain(addBuffers, name)
+    master_fixer.node :=* out
+    in
+  }
+
+  def fromSyncFIFOMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
+    val (in, out) = bufferChain(addBuffers, name)
+    master_fixer.node :=* out
+    in
+  }
+
+  def fromCoherentChip: TLInwardNode = inwardNode
 
   def toSystemBus : TLOutwardNode = outwardBufNode
 
@@ -43,8 +54,8 @@ trait HasFrontBus extends HasSystemBus {
   private val frontbusParams = p(FrontBusParams)
   val frontbusBeatBytes = frontbusParams.beatBytes
 
-  val frontbus = new FrontBus(frontbusParams)
+  val fbus = new FrontBus(frontbusParams)
 
-  sbus.fromSyncPorts(name = Some("FrontBus")) := frontbus.toSystemBus
+  sbus.bufferFromMasters := fbus.toSystemBus
 
 }

From a902e159877cf94eee3af0d47b50a97c79e12613 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Fri, 1 Sep 2017 18:18:13 -0700
Subject: [PATCH 15/20] pbus: clarify that we are adding buffers when attaching
 to sbus

---
 src/main/scala/coreplex/PeripheryBus.scala | 2 +-
 src/main/scala/coreplex/SystemBus.scala    | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala
index 7e51691e..7cbbdb56 100644
--- a/src/main/scala/coreplex/PeripheryBus.scala
+++ b/src/main/scala/coreplex/PeripheryBus.scala
@@ -48,5 +48,5 @@ trait HasPeripheryBus extends HasSystemBus {
   val pbus = new PeripheryBus(pbusParams)
 
   // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
-  pbus.fromSystemBus := sbus.toPeripheryBus(nBuffers = 1)
+  pbus.fromSystemBus := sbus.toPeripheryBus(addBuffers = 1)
 }
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index f3022731..35cfb1c6 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -37,8 +37,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def toSplitSlaves: TLOutwardNode = outwardSplitNode
 
-  def toPeripheryBus(nBuffers: Int): TLOutwardNode = {
-    val (in, out) = bufferChain(nBuffers, name = Some("pbus"))
+  def toPeripheryBus(addBuffers: Int): TLOutwardNode = {
+    val (in, out) = bufferChain(addBuffers, name = Some("pbus"))
     in := pbus_fixer.node
     out
   }

From 5886025b1a2ec10c8bea501135dfc771d2ed277a Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Tue, 5 Sep 2017 13:33:34 -0700
Subject: [PATCH 16/20] sbus => pbus: 2 buffers should already be enough

There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.

Between them is only an AtomicAutomata.
That should be enough for most designs.
---
 src/main/scala/coreplex/PeripheryBus.scala | 2 +-
 src/main/scala/coreplex/SystemBus.scala    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala
index 7cbbdb56..04ec0338 100644
--- a/src/main/scala/coreplex/PeripheryBus.scala
+++ b/src/main/scala/coreplex/PeripheryBus.scala
@@ -48,5 +48,5 @@ trait HasPeripheryBus extends HasSystemBus {
   val pbus = new PeripheryBus(pbusParams)
 
   // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
-  pbus.fromSystemBus := sbus.toPeripheryBus(addBuffers = 1)
+  pbus.fromSystemBus := sbus.toPeripheryBus()
 }
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 35cfb1c6..6f0a371d 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -37,7 +37,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def toSplitSlaves: TLOutwardNode = outwardSplitNode
 
-  def toPeripheryBus(addBuffers: Int): TLOutwardNode = {
+  def toPeripheryBus(addBuffers: Int = 0): TLOutwardNode = {
     val (in, out) = bufferChain(addBuffers, name = Some("pbus"))
     in := pbus_fixer.node
     out

From e65f49b89ae0cdd38bca2bc632b403c4b5a5c8bb Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Tue, 5 Sep 2017 15:02:16 -0700
Subject: [PATCH 17/20] FrontBus: attach to splitter for cross-chip visibility

---
 src/main/scala/coreplex/FrontBus.scala  | 4 ++--
 src/main/scala/coreplex/SystemBus.scala | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 3fd080d9..6e4b3883 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -12,7 +12,7 @@ case class FrontBusParams(
   beatBytes: Int,
   blockBytes: Int,
   masterBuffering: BufferParams = BufferParams.default,
-  slaveBuffering: BufferParams = BufferParams.none
+  slaveBuffering: BufferParams = BufferParams.default
 ) extends TLBusParams
 
 case object FrontBusParams extends Field[FrontBusParams]
@@ -56,6 +56,6 @@ trait HasFrontBus extends HasSystemBus {
 
   val fbus = new FrontBus(frontbusParams)
 
-  sbus.bufferFromMasters := fbus.toSystemBus
+  sbus.fromFrontBus := fbus.toSystemBus
 
 }
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 6f0a371d..5b7b771b 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -49,6 +49,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def fromCoherentChip: TLInwardNode = inwardNode
 
+  def fromFrontBus: TLInwardNode = master_splitter.node
+
   def fromSyncTiles(params: BufferParams, addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
     val tile_buf = LazyModule(new TLBuffer(params))
     name.foreach { n => tile_buf.suggestName(s"${busName}_${n}_TLBuffer") }

From b74a419bfbb34f4ec2e56373386f701c31939245 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Tue, 5 Sep 2017 16:27:57 -0700
Subject: [PATCH 18/20] FrontBus: FIFOFixer should not have a buffer between it
 and Xbar

---
 src/main/scala/coreplex/FrontBus.scala | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 6e4b3883..e51732a0 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -19,25 +19,24 @@ case object FrontBusParams extends Field[FrontBusParams]
 
 class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") {
 
+  private val master_buffer = LazyModule(new TLBuffer(params.masterBuffering))
   private val master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
-  master_fixer.suggestName(s"${busName}_master_TLFIFOFixer")
-  inwardBufNode :=* master_fixer.node
 
-  def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
-    val (in, out) = bufferChain(addBuffers, name)
-    inwardBufNode :=* out
-    in
-  }
+  master_buffer.suggestName(s"${busName}_master_TLBuffer")
+  master_fixer.suggestName(s"${busName}_master_TLFIFOFixer")
+
+  master_fixer.node :=* master_buffer.node
+  inwardNode :=* master_fixer.node
 
   def fromSyncPorts(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
     val (in, out) = bufferChain(addBuffers, name)
-    master_fixer.node :=* out
+    master_buffer.node :=* out
     in
   }
 
-  def fromSyncFIFOMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
+  def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
     val (in, out) = bufferChain(addBuffers, name)
-    master_fixer.node :=* out
+    master_buffer.node :=* out
     in
   }
 

From b1cacc56ad26b2f35102ccd71d85df741a2a14df Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Tue, 5 Sep 2017 16:41:39 -0700
Subject: [PATCH 19/20] SystemBus: restore correct order of FIFOFixer and
 Buffer

---
 src/main/scala/coreplex/SystemBus.scala | 31 +++++++++++--------------
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 5b7b771b..94db58db 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -27,6 +27,10 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   protected def inwardSplitNode: TLInwardNode = master_splitter.node
   protected def outwardSplitNode: TLOutwardNode = master_splitter.node
 
+  private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
+  tile_fixer.suggestName(s"${busName}_tile_TLFIFOFixer")
+  master_splitter.node :=* tile_fixer.node
+
   private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
   port_fixer.suggestName(s"${busName}_port_TLFIFOFixer")
   master_splitter.node :=* port_fixer.node
@@ -54,45 +58,36 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   def fromSyncTiles(params: BufferParams, addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
     val tile_buf = LazyModule(new TLBuffer(params))
     name.foreach { n => tile_buf.suggestName(s"${busName}_${n}_TLBuffer") }
-    val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
-    name.foreach { n => tile_fixer.suggestName(s"${busName}_${n}_TLFIFOFixer") }
     val (in, out) = bufferChain(addBuffers, name = name)
 
-    master_splitter.node :=* out
-    in :=* tile_fixer.node
-    tile_fixer.node :=* tile_buf.node
+    tile_fixer.node :=* out
+    in :=* tile_buf.node
     tile_buf.node
   }
 
   def fromRationalTiles(dir: RationalDirection, addBuffers: Int = 0, name: Option[String] = None): TLRationalInwardNode = {
     val tile_sink = LazyModule(new TLRationalCrossingSink(direction = dir))
-    name.foreach{ n => tile_sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
-    val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
-    name.foreach { n => tile_fixer.suggestName(s"${busName}_${n}_TLFIFOFixer") }
+    name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
     val (in, out) = bufferChain(addBuffers, name = name)
 
-    master_splitter.node :=* out
-    in :=* tile_fixer.node
-    tile_fixer.node :=* tile_sink.node
+    tile_fixer.node :=* out
+    in :=* tile_sink.node
     tile_sink.node
   }
 
   def fromAsyncTiles(depth: Int, sync: Int, addBuffers: Int = 0, name: Option[String] = None): TLAsyncInwardNode = {
     val tile_sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
     name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
-    val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
-    name.foreach { n => tile_fixer.suggestName(s"${busName}_${n}_TLFIFOFixer") }
     val (in, out) = bufferChain(addBuffers, name = name)
 
-    master_splitter.node :=* out
-    in :=* tile_fixer.node
-    tile_fixer.node :=* tile_sink.node
+    tile_fixer.node :=* out
+    in :=* tile_sink.node
     tile_sink.node
   }
 
   def fromSyncPorts(params: BufferParams =  BufferParams.default, name: Option[String] = None): TLInwardNode = {
     val buffer = LazyModule(new TLBuffer(params))
-    name.foreach{ n => buffer.suggestName(s"${busName}_${n}_TLBuffer") }
+    name.foreach { n => buffer.suggestName(s"${busName}_${n}_TLBuffer") }
     port_fixer.node :=* buffer.node
     buffer.node
   }
@@ -103,7 +98,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def fromAsyncPorts(depth: Int = 8, sync: Int = 3, name : Option[String] = None): TLAsyncInwardNode = {
     val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
-    name.foreach{ n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
+    name.foreach { n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
     port_fixer.node :=* sink.node
     sink.node
   }

From f1b7666d21e1a6df17cd3093c15492deacde9a3d Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Wed, 6 Sep 2017 09:49:47 -0700
Subject: [PATCH 20/20] Jtagresettobool - add explicit toBool cast now required
 on reset. (#984)

Add explicit toBool cast on reset, for chisel3 compatability
---
 src/main/scala/jtag/JtagTap.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/jtag/JtagTap.scala b/src/main/scala/jtag/JtagTap.scala
index 8470e9d9..78468582 100644
--- a/src/main/scala/jtag/JtagTap.scala
+++ b/src/main/scala/jtag/JtagTap.scala
@@ -100,7 +100,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt) extends Modul
   val nextActiveInstruction = Wire(UInt(irLength.W))
   val activeInstruction = NegativeEdgeLatch(clock, nextActiveInstruction, updateInstruction, name = Some("irReg"))   // 7.2.1d active instruction output latches on TCK falling edge
 
-  when (reset) {
+  when (reset.toBool) {
     nextActiveInstruction := initialInstruction.U(irLength.W)
     updateInstruction := true.B
   } .elsewhen (currState === JtagState.UpdateIR.U) {