Add TLB miss performance counters (#762)
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@ -56,8 +56,7 @@ class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
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resp.valid := io.mem.resp.valid && tag_hit
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io.requestor(i).s2_xcpt := io.mem.s2_xcpt
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io.requestor(i).ordered := io.mem.ordered
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io.requestor(i).acquire := io.mem.acquire
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io.requestor(i).release := io.mem.release
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io.requestor(i).perf := io.mem.perf
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io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === UInt(i)
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resp.bits := io.mem.resp.bits
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resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n)
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@ -142,6 +142,7 @@ object CSR
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val firstHPM = 3
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val nCtr = 32
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val nHPM = nCtr - firstHPM
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val hpmWidth = 40
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val maxPMPs = 16
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}
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@ -290,7 +291,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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val reg_cycle = if (enableCommitLog) reg_instret else WideCounter(64)
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val reg_hpmevent = io.counters.map(c => Reg(init = UInt(0, xLen)))
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(io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e }
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val reg_hpmcounter = io.counters.map(c => WideCounter(40, c.inc, reset = false))
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val reg_hpmcounter = io.counters.map(c => WideCounter(CSR.hpmWidth, c.inc, reset = false))
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val hpm_mask = reg_mcounteren & Mux((!usingVM).B || reg_mstatus.prv === PRV.S, delegable_counters.U, reg_scounteren)
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val mip = Wire(init=reg_mip)
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@ -562,6 +562,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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// performance events
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io.cpu.acquire := edge.done(tl_out_a)
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io.cpu.release := edge.done(tl_out.c)
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io.cpu.perf.acquire := edge.done(tl_out_a)
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io.cpu.perf.release := edge.done(tl_out.c)
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io.cpu.perf.tlbMiss := io.ptw.req.fire()
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}
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@ -28,6 +28,11 @@ class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
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val replay = Bool()
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}
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class FrontendPerfEvents extends Bundle {
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val acquire = Bool()
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val tlbMiss = Bool()
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}
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class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
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val req = Valid(new FrontendReq)
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val sfence = Valid(new SFenceReq)
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@ -37,9 +42,7 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
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val ras_update = Valid(new RASUpdate)
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val flush_icache = Bool(OUTPUT)
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val npc = UInt(INPUT, width = vaddrBitsExtended)
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// performance events
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val acquire = Bool(INPUT)
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val perf = new FrontendPerfEvents().asInput
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}
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class Frontend(hartid: Int)(implicit p: Parameters) extends LazyModule {
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@ -175,7 +178,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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io.cpu.resp <> fq.io.deq
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// performance events
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io.cpu.acquire := edge.done(icache.io.tl_out(0).a)
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io.cpu.perf.acquire := edge.done(icache.io.tl_out(0).a)
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io.cpu.perf.tlbMiss := io.ptw.req.fire()
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}
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/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
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@ -124,6 +124,12 @@ class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) {
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val mask = UInt(width = coreDataBytes)
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}
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class HellaCachePerfEvents extends Bundle {
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val acquire = Bool()
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val release = Bool()
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val tlbMiss = Bool()
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}
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// interface between D$ and processor/DTLB
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class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
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val req = Decoupled(new HellaCacheReq)
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@ -131,15 +137,12 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
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val s1_data = new HellaCacheWriteData().asOutput // data for previous cycle's req
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val s2_nack = Bool(INPUT) // req from two cycles ago is rejected
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// performance events
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val acquire = Bool(INPUT)
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val release = Bool(INPUT)
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val resp = Valid(new HellaCacheResp).flip
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val replay_next = Bool(INPUT)
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val s2_xcpt = (new HellaCacheExceptions).asInput
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val invalidate_lr = Bool(OUTPUT)
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val ordered = Bool(INPUT)
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val perf = new HellaCachePerfEvents().asInput
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}
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/** Base classes for Diplomatic TL2 HellaCaches */
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@ -985,6 +985,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
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io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), RegEnable(s1_xcpt, s1_clk_en), 0.U.asTypeOf(s1_xcpt))
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// performance events
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io.cpu.acquire := edge.done(tl_out.a)
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io.cpu.release := edge.done(tl_out.c)
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io.cpu.perf.acquire := edge.done(tl_out.a)
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io.cpu.perf.release := edge.done(tl_out.c)
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io.cpu.perf.tlbMiss := io.ptw.req.fire()
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}
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@ -102,9 +102,11 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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++ (if (!usingFPU) Seq() else Seq(
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("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))),
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new EventSet((mask, hits) => (mask & hits).orR, Seq(
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("I$ miss", () => io.imem.acquire),
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("D$ miss", () => io.dmem.acquire),
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("D$ release", () => io.dmem.release)))))
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("I$ miss", () => io.imem.perf.acquire),
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("D$ miss", () => io.dmem.perf.acquire),
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("D$ release", () => io.dmem.perf.release),
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("ITLB miss", () => io.imem.perf.tlbMiss),
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("DTLB miss", () => io.dmem.perf.tlbMiss)))))
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val decode_table = {
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(if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++:
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