riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Add TLB miss performance counters (#762)

Browse Source
This commit is contained in:
Andrew Waterman
2017-05-23 12:52:25 -07:00
committed by Henry Cook
parent b2b4c1abcd
commit dbc5e7c494
7 changed files with 29 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/rocket/NBDcache.scala
View File

@ -985,6 +985,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), RegEnable(s1_xcpt, s1_clk_en), 0.U.asTypeOf(s1_xcpt))
// performance events
io.cpu.acquire := edge.done(tl_out.a)
io.cpu.release := edge.done(tl_out.c)
io.cpu.perf.acquire := edge.done(tl_out.a)
io.cpu.perf.release := edge.done(tl_out.c)
io.cpu.perf.tlbMiss := io.ptw.req.fire()
}