riscv/rocket-chip
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Add TLB miss performance counters (#762)

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This commit is contained in:
Andrew Waterman
2017-05-23 12:52:25 -07:00
committed by Henry Cook
parent b2b4c1abcd
commit dbc5e7c494
7 changed files with 29 additions and 18 deletions
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12
src/main/scala/rocket/Frontend.scala
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@ -28,6 +28,11 @@ class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
val replay = Bool()
}
class FrontendPerfEvents extends Bundle {
val acquire = Bool()
val tlbMiss = Bool()
}
class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
val req = Valid(new FrontendReq)
val sfence = Valid(new SFenceReq)
@ -37,9 +42,7 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
val ras_update = Valid(new RASUpdate)
val flush_icache = Bool(OUTPUT)
val npc = UInt(INPUT, width = vaddrBitsExtended)
// performance events
val acquire = Bool(INPUT)
val perf = new FrontendPerfEvents().asInput
}
class Frontend(hartid: Int)(implicit p: Parameters) extends LazyModule {
@ -175,7 +178,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
io.cpu.resp <> fq.io.deq
// performance events
io.cpu.acquire := edge.done(icache.io.tl_out(0).a)
io.cpu.perf.acquire := edge.done(icache.io.tl_out(0).a)
io.cpu.perf.tlbMiss := io.ptw.req.fire()
}
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */