riscv/rocket-chip
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Add TLB miss performance counters (#762)

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This commit is contained in:
Andrew Waterman
2017-05-23 12:52:25 -07:00
committed by Henry Cook
parent b2b4c1abcd
commit dbc5e7c494
7 changed files with 29 additions and 18 deletions
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5
src/main/scala/rocket/DCache.scala
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@ -562,6 +562,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
}
// performance events
io.cpu.acquire := edge.done(tl_out_a)
io.cpu.release := edge.done(tl_out.c)
io.cpu.perf.acquire := edge.done(tl_out_a)
io.cpu.perf.release := edge.done(tl_out.c)
io.cpu.perf.tlbMiss := io.ptw.req.fire()
}