riscv/rocket-chip
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Add TLB miss performance counters (#762)

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This commit is contained in:
Andrew Waterman
2017-05-23 12:52:25 -07:00
committed by Henry Cook
parent b2b4c1abcd
commit dbc5e7c494
7 changed files with 29 additions and 18 deletions
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3
src/main/scala/rocket/CSR.scala
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@ -142,6 +142,7 @@ object CSR
val firstHPM = 3
val nCtr = 32
val nHPM = nCtr - firstHPM
val hpmWidth = 40
val maxPMPs = 16
}
@ -290,7 +291,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val reg_cycle = if (enableCommitLog) reg_instret else WideCounter(64)
val reg_hpmevent = io.counters.map(c => Reg(init = UInt(0, xLen)))
(io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e }
val reg_hpmcounter = io.counters.map(c => WideCounter(40, c.inc, reset = false))
val reg_hpmcounter = io.counters.map(c => WideCounter(CSR.hpmWidth, c.inc, reset = false))
val hpm_mask = reg_mcounteren & Mux((!usingVM).B || reg_mstatus.prv === PRV.S, delegable_counters.U, reg_scounteren)
val mip = Wire(init=reg_mip)