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Fragmenter: fix a bug when underlying device supports larger bursts (#589)

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This commit is contained in:
Wesley W. Terpstra
2017-03-17 11:00:49 -07:00
committed by GitHub
parent eb953c40f0
commit db55a1d755
1 changed files with 13 additions and 3 deletions
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16
src/main/scala/uncore/tilelink2/Fragmenter.scala
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@@ -129,7 +129,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else manager.maxTransfer
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// First, handle the return path
val acknum = RegInit(UInt(0, width = counterBits))
@@ -226,7 +226,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
repeater.io.repeat := !aHasData && aFragnum =/= UInt(0)
out.a <> in_a
out.a.bits.address := in_a.bits.address | (~aFragnum << log2Ceil(minSize) & aOrigOH1)
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | UInt(minSize-1))
out.a.bits.source := Cat(in_a.bits.source, aFragnum)
out.a.bits.size := aFrag
@@ -267,7 +267,17 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) e
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node
ram.node := TLDelayer(0.1)(TLFragmenter(ramBeatBytes, maxSize)(TLDelayer(0.1)(model.node)))
ram.node :=
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
TLDelayer(0.1)(
TLFragmenter(ramBeatBytes, maxSize)(
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
TLFragmenter(ramBeatBytes, maxSize/2)(
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
model.node)))))))))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished