riscv/rocket-chip
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WIP on priv-1.10

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This commit is contained in:
Andrew Waterman
2017-02-27 14:27:19 -08:00
parent 43dea38ee9
commit db0a02b78e
8 changed files with 101 additions and 111 deletions
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2
src/main/scala/tile/Core.scala
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@ -60,7 +60,7 @@ trait HasCoreParameters extends HasTileParameters {
val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
val maxPAddrBits = xLen match { case 32 => 34; case 64 => 50 }
val maxPAddrBits = xLen match { case 32 => 34; case 64 => 56 }
require(paddrBits <= maxPAddrBits)
// Print out log of committed instructions and their writeback values.