riscv/rocket-chip
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WIP on priv-1.10

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This commit is contained in:
Andrew Waterman
2017-02-27 14:27:19 -08:00
parent 43dea38ee9
commit db0a02b78e
8 changed files with 101 additions and 111 deletions
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2
src/main/scala/coreplex/Configs.scala
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@ -17,7 +17,7 @@ import util._
class BaseCoreplexConfig extends Config ((site, here, up) => {
case PAddrBits => 32
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
case ASIdBits => 7
case ASIdBits => 0
case XLen => 64 // Applies to all cores
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketCrossing => Synchronous