factor out common cache subcomponents into uncore.util
This commit is contained in:
Henry Cook
180
src/main/scala/uncore/util/Cache.scala
Normal file
180
src/main/scala/uncore/util/Cache.scala
Normal file
@ -0,0 +1,180 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package uncore.util
|
||||
|
||||
import Chisel._
|
||||
import config.{Parameters, Field}
|
||||
import junctions.PAddrBits
|
||||
import util.ParameterizedBundle
|
||||
import uncore.constants._
|
||||
|
||||
case class CacheConfig(
|
||||
nSets: Int,
|
||||
nWays: Int,
|
||||
rowBits: Int,
|
||||
nTLBEntries: Int,
|
||||
cacheIdBits: Int,
|
||||
splitMetadata: Boolean)
|
||||
case class CacheName(id: String) extends Field[CacheConfig]
|
||||
case object CacheName extends Field[CacheName]
|
||||
|
||||
case object Replacer extends Field[() => ReplacementPolicy]
|
||||
case object L2Replacer extends Field[() => SeqReplacementPolicy]
|
||||
case object NPrimaryMisses extends Field[Int]
|
||||
case object NSecondaryMisses extends Field[Int]
|
||||
case object CacheBlockBytes extends Field[Int]
|
||||
case object ECCCode extends Field[Option[Code]]
|
||||
|
||||
trait HasCacheParameters {
|
||||
implicit val p: Parameters
|
||||
val cacheConfig = p(p(CacheName))
|
||||
val nSets = cacheConfig.nSets
|
||||
val blockOffBits = log2Up(p(CacheBlockBytes))
|
||||
val cacheIdBits = cacheConfig.cacheIdBits
|
||||
val idxBits = log2Up(cacheConfig.nSets)
|
||||
val untagBits = blockOffBits + cacheIdBits + idxBits
|
||||
val tagBits = p(PAddrBits) - untagBits
|
||||
val nWays = cacheConfig.nWays
|
||||
val wayBits = log2Up(nWays)
|
||||
val isDM = nWays == 1
|
||||
val rowBits = cacheConfig.rowBits
|
||||
val rowBytes = rowBits/8
|
||||
val rowOffBits = log2Up(rowBytes)
|
||||
val code = p(ECCCode).getOrElse(new IdentityCode)
|
||||
val hasSplitMetadata = cacheConfig.splitMetadata
|
||||
}
|
||||
|
||||
abstract class CacheModule(implicit val p: Parameters) extends Module
|
||||
with HasCacheParameters
|
||||
abstract class CacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
|
||||
with HasCacheParameters
|
||||
|
||||
abstract class ReplacementPolicy {
|
||||
def way: UInt
|
||||
def miss: Unit
|
||||
def hit: Unit
|
||||
}
|
||||
|
||||
class RandomReplacement(ways: Int) extends ReplacementPolicy {
|
||||
private val replace = Wire(Bool())
|
||||
replace := Bool(false)
|
||||
val lfsr = LFSR16(replace)
|
||||
|
||||
def way = if(ways == 1) UInt(0) else lfsr(log2Up(ways)-1,0)
|
||||
def miss = replace := Bool(true)
|
||||
def hit = {}
|
||||
}
|
||||
|
||||
abstract class SeqReplacementPolicy {
|
||||
def access(set: UInt): Unit
|
||||
def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit
|
||||
def way: UInt
|
||||
}
|
||||
|
||||
class SeqRandom(n_ways: Int) extends SeqReplacementPolicy {
|
||||
val logic = new RandomReplacement(n_ways)
|
||||
def access(set: UInt) = { }
|
||||
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
|
||||
when (valid && !hit) { logic.miss }
|
||||
}
|
||||
def way = logic.way
|
||||
}
|
||||
|
||||
class PseudoLRU(n: Int)
|
||||
{
|
||||
require(isPow2(n))
|
||||
val state_reg = Reg(Bits(width = n))
|
||||
def access(way: UInt) {
|
||||
state_reg := get_next_state(state_reg,way)
|
||||
}
|
||||
def get_next_state(state: UInt, way: UInt) = {
|
||||
var next_state = state
|
||||
var idx = UInt(1,1)
|
||||
for (i <- log2Up(n)-1 to 0 by -1) {
|
||||
val bit = way(i)
|
||||
next_state = next_state.bitSet(idx, !bit)
|
||||
idx = Cat(idx, bit)
|
||||
}
|
||||
next_state
|
||||
}
|
||||
def replace = get_replace_way(state_reg)
|
||||
def get_replace_way(state: Bits) = {
|
||||
var idx = UInt(1,1)
|
||||
for (i <- 0 until log2Up(n))
|
||||
idx = Cat(idx, state(idx))
|
||||
idx(log2Up(n)-1,0)
|
||||
}
|
||||
}
|
||||
|
||||
class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
|
||||
val state = SeqMem(n_sets, Bits(width = n_ways-1))
|
||||
val logic = new PseudoLRU(n_ways)
|
||||
val current_state = Wire(Bits())
|
||||
val plru_way = logic.get_replace_way(current_state)
|
||||
val next_state = Wire(Bits())
|
||||
|
||||
def access(set: UInt) = {
|
||||
current_state := Cat(state.read(set), Bits(0, width = 1))
|
||||
}
|
||||
|
||||
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
|
||||
val update_way = Mux(hit, way, plru_way)
|
||||
next_state := logic.get_next_state(current_state, update_way)
|
||||
when (valid) { state.write(set, next_state(n_ways-1,1)) }
|
||||
}
|
||||
|
||||
def way = plru_way
|
||||
}
|
||||
|
||||
abstract class Metadata(implicit p: Parameters) extends CacheBundle()(p) {
|
||||
val tag = Bits(width = tagBits)
|
||||
}
|
||||
|
||||
class MetaReadReq(implicit p: Parameters) extends CacheBundle()(p) {
|
||||
val idx = Bits(width = idxBits)
|
||||
val way_en = Bits(width = nWays)
|
||||
}
|
||||
|
||||
class MetaWriteReq[T <: Metadata](gen: T)(implicit p: Parameters) extends MetaReadReq()(p) {
|
||||
val data = gen.cloneType
|
||||
override def cloneType = new MetaWriteReq(gen)(p).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) extends CacheModule()(p) {
|
||||
val rstVal = onReset()
|
||||
val io = new Bundle {
|
||||
val read = Decoupled(new MetaReadReq).flip
|
||||
val write = Decoupled(new MetaWriteReq(rstVal)).flip
|
||||
val resp = Vec(nWays, rstVal.cloneType).asOutput
|
||||
}
|
||||
val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
|
||||
val rst = rst_cnt < UInt(nSets)
|
||||
val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
|
||||
val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt
|
||||
val wmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.write.bits.way_en.asSInt).toBools
|
||||
val rmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.read.bits.way_en.asSInt).toBools
|
||||
when (rst) { rst_cnt := rst_cnt+UInt(1) }
|
||||
|
||||
val metabits = rstVal.getWidth
|
||||
|
||||
if (hasSplitMetadata) {
|
||||
val tag_arrs = List.fill(nWays){ SeqMem(nSets, UInt(width = metabits)) }
|
||||
val tag_readout = Wire(Vec(nWays,rstVal.cloneType))
|
||||
(0 until nWays).foreach { (i) =>
|
||||
when (rst || (io.write.valid && wmask(i))) {
|
||||
tag_arrs(i).write(waddr, wdata)
|
||||
}
|
||||
io.resp(i) := rstVal.fromBits(tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i)))
|
||||
}
|
||||
} else {
|
||||
val tag_arr = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
|
||||
when (rst || io.write.valid) {
|
||||
tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask)
|
||||
}
|
||||
io.resp := tag_arr.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
|
||||
}
|
||||
|
||||
io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
|
||||
io.write.ready := !rst
|
||||
}
|
||||
|
||||
146
src/main/scala/uncore/util/Ecc.scala
Normal file
146
src/main/scala/uncore/util/Ecc.scala
Normal file
@ -0,0 +1,146 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package uncore.util
|
||||
|
||||
import Chisel._
|
||||
import util._
|
||||
|
||||
abstract class Decoding
|
||||
{
|
||||
def uncorrected: UInt
|
||||
def corrected: UInt
|
||||
def correctable: Bool
|
||||
def uncorrectable: Bool
|
||||
def error = correctable || uncorrectable
|
||||
}
|
||||
|
||||
abstract class Code
|
||||
{
|
||||
def width(w0: Int): Int
|
||||
def encode(x: UInt): UInt
|
||||
def decode(x: UInt): Decoding
|
||||
}
|
||||
|
||||
class IdentityCode extends Code
|
||||
{
|
||||
def width(w0: Int) = w0
|
||||
def encode(x: UInt) = x
|
||||
def decode(y: UInt) = new Decoding {
|
||||
def uncorrected = y
|
||||
def corrected = y
|
||||
def correctable = Bool(false)
|
||||
def uncorrectable = Bool(false)
|
||||
}
|
||||
}
|
||||
|
||||
class ParityCode extends Code
|
||||
{
|
||||
def width(w0: Int) = w0+1
|
||||
def encode(x: UInt) = Cat(x.xorR, x)
|
||||
def decode(y: UInt) = new Decoding {
|
||||
def uncorrected = y(y.getWidth-2,0)
|
||||
def corrected = uncorrected
|
||||
def correctable = Bool(false)
|
||||
def uncorrectable = y.xorR
|
||||
}
|
||||
}
|
||||
|
||||
class SECCode extends Code
|
||||
{
|
||||
def width(k: Int) = {
|
||||
val m = log2Floor(k) + 1
|
||||
k + m + (if((1 << m) < m+k+1) 1 else 0)
|
||||
}
|
||||
def encode(x: UInt) = {
|
||||
val k = x.getWidth
|
||||
require(k > 0)
|
||||
val n = width(k)
|
||||
|
||||
val y = for (i <- 1 to n) yield {
|
||||
if (isPow2(i)) {
|
||||
val r = for (j <- 1 to n; if j != i && (j & i) != 0)
|
||||
yield x(mapping(j))
|
||||
r reduce (_^_)
|
||||
} else
|
||||
x(mapping(i))
|
||||
}
|
||||
y.asUInt
|
||||
}
|
||||
def decode(y: UInt) = new Decoding {
|
||||
val n = y.getWidth
|
||||
require(n > 0 && !isPow2(n))
|
||||
|
||||
val p2 = for (i <- 0 until log2Up(n)) yield 1 << i
|
||||
val syndrome = (p2 map { i =>
|
||||
val r = for (j <- 1 to n; if (j & i) != 0)
|
||||
yield y(j-1)
|
||||
r reduce (_^_)
|
||||
}).asUInt
|
||||
|
||||
private def swizzle(z: UInt) = (1 to n).filter(i => !isPow2(i)).map(i => z(i-1)).asUInt
|
||||
def uncorrected = swizzle(y)
|
||||
def corrected = swizzle(((y << 1) ^ UIntToOH(syndrome)) >> 1)
|
||||
def correctable = syndrome.orR
|
||||
def uncorrectable = Bool(false)
|
||||
}
|
||||
private def mapping(i: Int) = i-1-log2Up(i)
|
||||
}
|
||||
|
||||
class SECDEDCode extends Code
|
||||
{
|
||||
private val sec = new SECCode
|
||||
private val par = new ParityCode
|
||||
|
||||
def width(k: Int) = sec.width(k)+1
|
||||
def encode(x: UInt) = par.encode(sec.encode(x))
|
||||
def decode(x: UInt) = new Decoding {
|
||||
val secdec = sec.decode(x(x.getWidth-2,0))
|
||||
val pardec = par.decode(x)
|
||||
|
||||
def uncorrected = secdec.uncorrected
|
||||
def corrected = secdec.corrected
|
||||
def correctable = pardec.uncorrectable
|
||||
def uncorrectable = !pardec.uncorrectable && secdec.correctable
|
||||
}
|
||||
}
|
||||
|
||||
object ErrGen
|
||||
{
|
||||
// generate a 1-bit error with approximate probability 2^-f
|
||||
def apply(width: Int, f: Int): UInt = {
|
||||
require(width > 0 && f >= 0 && log2Up(width) + f <= 16)
|
||||
UIntToOH(LFSR16()(log2Up(width)+f-1,0))(width-1,0)
|
||||
}
|
||||
def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f)
|
||||
}
|
||||
|
||||
class SECDEDTest extends Module
|
||||
{
|
||||
val code = new SECDEDCode
|
||||
val k = 4
|
||||
val n = code.width(k)
|
||||
|
||||
val io = new Bundle {
|
||||
val original = Bits(OUTPUT, k)
|
||||
val encoded = Bits(OUTPUT, n)
|
||||
val injected = Bits(OUTPUT, n)
|
||||
val uncorrected = Bits(OUTPUT, k)
|
||||
val corrected = Bits(OUTPUT, k)
|
||||
val correctable = Bool(OUTPUT)
|
||||
val uncorrectable = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
val c = Counter(Bool(true), 1 << k)
|
||||
val numErrors = Counter(c._2, 3)._1
|
||||
val e = code.encode(c._1)
|
||||
val i = e ^ Mux(numErrors < UInt(1), UInt(0), ErrGen(n, 1)) ^ Mux(numErrors < UInt(2), UInt(0), ErrGen(n, 1))
|
||||
val d = code.decode(i)
|
||||
|
||||
io.original := c._1
|
||||
io.encoded := e
|
||||
io.injected := i
|
||||
io.uncorrected := d.uncorrected
|
||||
io.corrected := d.corrected
|
||||
io.correctable := d.correctable
|
||||
io.uncorrectable := d.uncorrectable
|
||||
}
|
||||
Reference in New Issue
Block a user