factor out common cache subcomponents into uncore.util
This commit is contained in:
Henry Cook
@ -1,146 +0,0 @@
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// See LICENSE for license details.
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package uncore.agents
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import Chisel._
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import util._
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abstract class Decoding
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{
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def uncorrected: UInt
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def corrected: UInt
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def correctable: Bool
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def uncorrectable: Bool
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def error = correctable || uncorrectable
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}
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abstract class Code
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{
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def width(w0: Int): Int
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def encode(x: UInt): UInt
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def decode(x: UInt): Decoding
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}
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class IdentityCode extends Code
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{
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def width(w0: Int) = w0
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def encode(x: UInt) = x
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def decode(y: UInt) = new Decoding {
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def uncorrected = y
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def corrected = y
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def correctable = Bool(false)
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def uncorrectable = Bool(false)
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}
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}
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class ParityCode extends Code
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{
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def width(w0: Int) = w0+1
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def encode(x: UInt) = Cat(x.xorR, x)
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def decode(y: UInt) = new Decoding {
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def uncorrected = y(y.getWidth-2,0)
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def corrected = uncorrected
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def correctable = Bool(false)
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def uncorrectable = y.xorR
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}
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}
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class SECCode extends Code
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{
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def width(k: Int) = {
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val m = log2Floor(k) + 1
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k + m + (if((1 << m) < m+k+1) 1 else 0)
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}
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def encode(x: UInt) = {
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val k = x.getWidth
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require(k > 0)
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val n = width(k)
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val y = for (i <- 1 to n) yield {
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if (isPow2(i)) {
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val r = for (j <- 1 to n; if j != i && (j & i) != 0)
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yield x(mapping(j))
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r reduce (_^_)
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} else
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x(mapping(i))
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}
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y.asUInt
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}
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def decode(y: UInt) = new Decoding {
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val n = y.getWidth
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require(n > 0 && !isPow2(n))
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val p2 = for (i <- 0 until log2Up(n)) yield 1 << i
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val syndrome = (p2 map { i =>
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val r = for (j <- 1 to n; if (j & i) != 0)
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yield y(j-1)
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r reduce (_^_)
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}).asUInt
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private def swizzle(z: UInt) = (1 to n).filter(i => !isPow2(i)).map(i => z(i-1)).asUInt
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def uncorrected = swizzle(y)
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def corrected = swizzle(((y << 1) ^ UIntToOH(syndrome)) >> 1)
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def correctable = syndrome.orR
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def uncorrectable = Bool(false)
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}
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private def mapping(i: Int) = i-1-log2Up(i)
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}
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class SECDEDCode extends Code
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{
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private val sec = new SECCode
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private val par = new ParityCode
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def width(k: Int) = sec.width(k)+1
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def encode(x: UInt) = par.encode(sec.encode(x))
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def decode(x: UInt) = new Decoding {
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val secdec = sec.decode(x(x.getWidth-2,0))
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val pardec = par.decode(x)
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def uncorrected = secdec.uncorrected
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def corrected = secdec.corrected
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def correctable = pardec.uncorrectable
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def uncorrectable = !pardec.uncorrectable && secdec.correctable
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}
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}
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object ErrGen
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{
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// generate a 1-bit error with approximate probability 2^-f
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def apply(width: Int, f: Int): UInt = {
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require(width > 0 && f >= 0 && log2Up(width) + f <= 16)
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UIntToOH(LFSR16()(log2Up(width)+f-1,0))(width-1,0)
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}
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def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f)
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}
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class SECDEDTest extends Module
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{
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val code = new SECDEDCode
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val k = 4
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val n = code.width(k)
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val io = new Bundle {
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val original = Bits(OUTPUT, k)
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val encoded = Bits(OUTPUT, n)
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val injected = Bits(OUTPUT, n)
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val uncorrected = Bits(OUTPUT, k)
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val corrected = Bits(OUTPUT, k)
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val correctable = Bool(OUTPUT)
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val uncorrectable = Bool(OUTPUT)
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}
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val c = Counter(Bool(true), 1 << k)
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val numErrors = Counter(c._2, 3)._1
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val e = code.encode(c._1)
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val i = e ^ Mux(numErrors < UInt(1), UInt(0), ErrGen(n, 1)) ^ Mux(numErrors < UInt(2), UInt(0), ErrGen(n, 1))
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val d = code.decode(i)
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io.original := c._1
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io.encoded := e
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io.injected := i
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io.uncorrected := d.uncorrected
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io.corrected := d.corrected
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io.correctable := d.correctable
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io.uncorrectable := d.uncorrectable
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}
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@ -5,186 +5,14 @@ package uncore.agents
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import Chisel._
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import scala.reflect.ClassTag
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import junctions.PAddrBits
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import util.ParameterizedBundle
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import uncore.util.AMOALU
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import uncore.coherence._
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import uncore.tilelink._
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import uncore.constants._
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import uncore.util._
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import util._
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import config._
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import config.{Parameters, Field}
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case class CacheConfig(
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nSets: Int,
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nWays: Int,
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rowBits: Int,
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nTLBEntries: Int,
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cacheIdBits: Int,
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splitMetadata: Boolean)
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case class CacheName(id: String) extends Field[CacheConfig]
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case object CacheName extends Field[CacheName]
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case object Replacer extends Field[() => ReplacementPolicy]
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case object L2Replacer extends Field[() => SeqReplacementPolicy]
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case object NPrimaryMisses extends Field[Int]
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case object NSecondaryMisses extends Field[Int]
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case object CacheBlockBytes extends Field[Int]
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case object ECCCode extends Field[Option[Code]]
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case object CacheId extends Field[Int]
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trait HasCacheParameters {
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implicit val p: Parameters
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val cacheConfig = p(p(CacheName))
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val nSets = cacheConfig.nSets
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val blockOffBits = p(CacheBlockOffsetBits)
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val cacheIdBits = cacheConfig.cacheIdBits
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val idxBits = log2Up(cacheConfig.nSets)
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val untagBits = blockOffBits + cacheIdBits + idxBits
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val tagBits = p(PAddrBits) - untagBits
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val nWays = cacheConfig.nWays
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val wayBits = log2Up(nWays)
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val isDM = nWays == 1
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val rowBits = cacheConfig.rowBits
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val rowBytes = rowBits/8
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val rowOffBits = log2Up(rowBytes)
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val code = p(ECCCode).getOrElse(new IdentityCode)
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val hasSplitMetadata = cacheConfig.splitMetadata
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}
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abstract class CacheModule(implicit val p: Parameters) extends Module
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with HasCacheParameters
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abstract class CacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasCacheParameters
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abstract class ReplacementPolicy {
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def way: UInt
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def miss: Unit
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def hit: Unit
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}
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class RandomReplacement(ways: Int) extends ReplacementPolicy {
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private val replace = Wire(Bool())
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replace := Bool(false)
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val lfsr = LFSR16(replace)
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def way = if(ways == 1) UInt(0) else lfsr(log2Up(ways)-1,0)
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def miss = replace := Bool(true)
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def hit = {}
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}
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abstract class SeqReplacementPolicy {
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def access(set: UInt): Unit
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def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit
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def way: UInt
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}
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class SeqRandom(n_ways: Int) extends SeqReplacementPolicy {
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val logic = new RandomReplacement(n_ways)
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def access(set: UInt) = { }
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def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
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when (valid && !hit) { logic.miss }
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}
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def way = logic.way
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}
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class PseudoLRU(n: Int)
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{
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require(isPow2(n))
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val state_reg = Reg(Bits(width = n))
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def access(way: UInt) {
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state_reg := get_next_state(state_reg,way)
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}
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def get_next_state(state: UInt, way: UInt) = {
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var next_state = state
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var idx = UInt(1,1)
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for (i <- log2Up(n)-1 to 0 by -1) {
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val bit = way(i)
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next_state = next_state.bitSet(idx, !bit)
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idx = Cat(idx, bit)
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}
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next_state
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}
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def replace = get_replace_way(state_reg)
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def get_replace_way(state: Bits) = {
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var idx = UInt(1,1)
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for (i <- 0 until log2Up(n))
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idx = Cat(idx, state(idx))
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idx(log2Up(n)-1,0)
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}
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}
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class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
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val state = SeqMem(n_sets, Bits(width = n_ways-1))
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val logic = new PseudoLRU(n_ways)
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val current_state = Wire(Bits())
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val plru_way = logic.get_replace_way(current_state)
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val next_state = Wire(Bits())
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def access(set: UInt) = {
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current_state := Cat(state.read(set), Bits(0, width = 1))
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}
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def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
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val update_way = Mux(hit, way, plru_way)
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next_state := logic.get_next_state(current_state, update_way)
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when (valid) { state.write(set, next_state(n_ways-1,1)) }
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}
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def way = plru_way
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}
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abstract class Metadata(implicit p: Parameters) extends CacheBundle()(p) {
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val tag = Bits(width = tagBits)
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}
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class MetaReadReq(implicit p: Parameters) extends CacheBundle()(p) {
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val idx = Bits(width = idxBits)
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val way_en = Bits(width = nWays)
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}
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class MetaWriteReq[T <: Metadata](gen: T)(implicit p: Parameters) extends MetaReadReq()(p) {
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val data = gen.cloneType
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override def cloneType = new MetaWriteReq(gen)(p).asInstanceOf[this.type]
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}
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class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) extends CacheModule()(p) {
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val rstVal = onReset()
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val io = new Bundle {
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val read = Decoupled(new MetaReadReq).flip
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val write = Decoupled(new MetaWriteReq(rstVal)).flip
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val resp = Vec(nWays, rstVal.cloneType).asOutput
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}
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val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
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val rst = rst_cnt < UInt(nSets)
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val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
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val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt
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val wmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.write.bits.way_en.asSInt).toBools
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val rmask = Mux(rst || Bool(nWays == 1), SInt(-1), io.read.bits.way_en.asSInt).toBools
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when (rst) { rst_cnt := rst_cnt+UInt(1) }
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val metabits = rstVal.getWidth
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if (hasSplitMetadata) {
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val tag_arrs = List.fill(nWays){ SeqMem(nSets, UInt(width = metabits)) }
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val tag_readout = Wire(Vec(nWays,rstVal.cloneType))
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(0 until nWays).foreach { (i) =>
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when (rst || (io.write.valid && wmask(i))) {
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tag_arrs(i).write(waddr, wdata)
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}
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io.resp(i) := rstVal.fromBits(tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i)))
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}
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} else {
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val tag_arr = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
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when (rst || io.write.valid) {
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tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask)
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}
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io.resp := tag_arr.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
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}
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io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
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io.write.ready := !rst
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}
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case object L2DirectoryRepresentation extends Field[DirectoryRepresentation]
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trait HasOuterCacheParameters extends HasCacheParameters with HasCoherenceAgentParameters {
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