From daa0f3038f4483aa9f1798dc6ca4f1e962cabc5b Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Mon, 20 Jun 2016 11:18:47 -0700
Subject: [PATCH] invoke firrtl jar directly in order to control heap memory
 usage

---
 Makefrag                    | 6 ++++++
 emulator/Makefrag-verilator | 7 +------
 vsim/Makefrag-verilog       | 7 +------
 3 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/Makefrag b/Makefrag
index c5401d83..dcf52542 100644
--- a/Makefrag
+++ b/Makefrag
@@ -14,6 +14,12 @@ export CHISEL_VERSION
 SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(base_dir)/sbt-launch.jar
 SHELL := /bin/bash
 
+FIRRTL_JAR ?= $(base_dir)/firrtl/utils/bin/firrtl.jar
+FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
+
+$(FIRRTL_JAR):
+	$(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala
+
 ifeq ($(CHISEL_VERSION),2)
 CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
 else
diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator
index 9c8f1bcf..efa78f9e 100644
--- a/emulator/Makefrag-verilator
+++ b/emulator/Makefrag-verilator
@@ -7,11 +7,6 @@ firrtl_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
 verilog = $(generated_dir)/$(MODEL).$(CONFIG).v
 verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v
 
-FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl
-
-$(FIRRTL):
-	$(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala
-
 .SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
 
 $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
@@ -24,7 +19,7 @@ $(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(
 	cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir_debug)"
 	mv $(generated_dir_debug)/$(MODEL).fir $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
 
-%.v: %.fir $(FIRRTL)
+%.v: %.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
 	$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog
 
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index f91c08d6..f50a902b 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -12,11 +12,6 @@ $(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).d $(ge
 
 else
 
-FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl
-
-$(FIRRTL):
-	$(MAKE) -C $(base_dir)/firrtl SBT="$(SBT)" root_dir=$(base_dir)/firrtl build-scala
-
 # If I don't mark these as .SECONDARY then make will delete these internal
 # files.
 .SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
@@ -26,7 +21,7 @@ $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
 	cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(patsubst %.d,%.fir,$(notdir $@))) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem"
 	mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
 
-$(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL)
+$(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
 	$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog