coreplex: TileLink2 l1tol2 memory channels

src/main/scala/coreplex/BaseCoreplex.scala

@@ -18,6 +18,8 @@ import util._
 case object NMemoryChannels extends Field[Int]
 /** Number of banks per memory channel */
 case object NBanksPerMemoryChannel extends Field[Int]
+/** Number of tracker per bank */
+case object NTrackersPerBank extends Field[Int]
 /** Least significant bit of address used for bank partitioning */
 case object BankIdLSB extends Field[Int]
 /** Function for building some kind of coherence manager agent */
@@ -39,6 +41,7 @@ trait HasCoreplexParameters {
   lazy val nSlaves = p(rocketchip.NCoreplexExtClients)
   lazy val nMemChannels = p(NMemoryChannels)
   lazy val hasSupervisor = p(rocket.UseVM)
+  lazy val nTrackersPerBank = p(NTrackersPerBank)
 }
 
 case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
@@ -93,6 +96,45 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
   implicit val p = outer.p
 }
 
+trait BankedL2 {
+    this: CoreplexNetwork =>
+  require (isPow2(nBanksPerMemChannel))
+  require (isPow2(l1tol2_beatBytes))
+
+  def l2ManagerFactory(): (TLInwardNode, TLOutwardNode)
+
+  val l2Channels = Seq.fill(nMemChannels) {
+    val bankBar = LazyModule(new TLXbar)
+    val output = TLOutputNode()
+
+    output := bankBar.node
+    val mask = ~BigInt((nBanksPerMemChannel-1) * l1tol2_lineBytes)
+    for (i <- 0 until nBanksPerMemChannel) {
+      val (in, out) = l2ManagerFactory()
+      in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node)
+      bankBar.node := out
+    }
+
+    output
+  }
+}
+
+trait BankedL2Bundle {
+  this: CoreplexNetworkBundle {
+    val outer: BankedL2
+  } =>
+
+  require (nMemChannels == 1, "Seq in Chisel Bundle needed to support > 1") // !!!
+  val mem = outer.l2Channels.map(_.bundleOut).toList.head // .head should be removed !!!
+}
+
+trait BankedL2Module {
+  this: CoreplexNetworkModule {
+    val outer: BankedL2
+    val io: BankedL2Bundle
+  } =>
+}
+
 trait CoreplexRISCVPlatform {
     this: CoreplexNetwork =>
 

src/main/scala/coreplex/Configs.scala

@@ -155,6 +155,7 @@ class BaseCoreplexConfig extends Config (
       case BootROMFile => "./bootrom/bootrom.img"
       case NTiles => 1
       case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
+      case NTrackersPerBank => Knob("NTRACKERS_PER_BANK")
       case BankIdLSB => 0
       case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
       case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
@@ -163,6 +164,7 @@ class BaseCoreplexConfig extends Config (
   }},
   knobValues = {
     case "NBANKS_PER_MEM_CHANNEL" => 1
+    case "NTRACKERS_PER_BANK" => 4
     case "L1D_MSHRS" => 2
     case "L1D_SETS" => 64
     case "L1D_WAYS" => 4
@@ -183,6 +185,12 @@ class WithNBanksPerMemChannel(n: Int) extends Config(
     case _ => throw new CDEMatchError
   })
 
+class WithNTrackersPerBank(n: Int) extends Config(
+  knobValues = {
+    case "NTRACKERS_PER_BANK" => n
+    case _ => throw new CDEMatchError
+  })
+
 class WithDataScratchpad(n: Int) extends Config(
   (pname,site,here) => pname match {
     case DataScratchpadSize => n

src/main/scala/coreplex/Coreplex.scala

@@ -10,6 +10,16 @@ import uncore.util._
 import util._
 import rocket._
 
+trait BroadcastL2 {
+    this: CoreplexNetwork =>
+  def l2ManagerFactory() = {
+    val bh = LazyModule(new TLBroadcast(l1tol2_beatBytes, nTrackersPerBank))
+    (bh.node, bh.node)
+  }
+}
+
+/////
+
 trait DirectConnection {
     this: CoreplexNetwork with CoreplexRISCVPlatform =>
   lazyTiles.map(_.slave).flatten.foreach { scratch => scratch := cbus.node }