coreplex: TileLink2 l1tol2 memory channels

2016-11-03 19:48:05 -07:00
parent 0f3947bb86
commit da3cc3b299
3 changed files with 60 additions and 0 deletions
--- a/src/main/scala/coreplex/Coreplex.scala
+++ b/src/main/scala/coreplex/Coreplex.scala
@ -10,6 +10,16 @@ import uncore.util._
 import util._
 import rocket._

+trait BroadcastL2 {
+    this: CoreplexNetwork =>
+  def l2ManagerFactory() = {
+    val bh = LazyModule(new TLBroadcast(l1tol2_beatBytes, nTrackersPerBank))
+    (bh.node, bh.node)
+  }
+}
+
+/////
+
 trait DirectConnection {
    this: CoreplexNetwork with CoreplexRISCVPlatform =>
  lazyTiles.map(_.slave).flatten.foreach { scratch => scratch := cbus.node }