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coreplex: TileLink2 l1tol2 memory channels

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This commit is contained in:
Wesley W. Terpstra
2016-11-03 19:48:05 -07:00
parent 0f3947bb86
commit da3cc3b299
3 changed files with 60 additions and 0 deletions
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8
src/main/scala/coreplex/Configs.scala
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@ -155,6 +155,7 @@ class BaseCoreplexConfig extends Config (
case BootROMFile => "./bootrom/bootrom.img"
case NTiles => 1
case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
case NTrackersPerBank => Knob("NTRACKERS_PER_BANK")
case BankIdLSB => 0
case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
@ -163,6 +164,7 @@ class BaseCoreplexConfig extends Config (
}},
knobValues = {
case "NBANKS_PER_MEM_CHANNEL" => 1
case "NTRACKERS_PER_BANK" => 4
case "L1D_MSHRS" => 2
case "L1D_SETS" => 64
case "L1D_WAYS" => 4
@ -183,6 +185,12 @@ class WithNBanksPerMemChannel(n: Int) extends Config(
case _ => throw new CDEMatchError
})
class WithNTrackersPerBank(n: Int) extends Config(
knobValues = {
case "NTRACKERS_PER_BANK" => n
case _ => throw new CDEMatchError
})
class WithDataScratchpad(n: Int) extends Config(
(pname,site,here) => pname match {
case DataScratchpadSize => n