riscv/rocket-chip
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Begin integer unit clean-up

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...to make it easier to generate the superscalar version of the core.
This commit is contained in:
Andrew Waterman
2013-12-09 15:06:13 -08:00
parent 16d5250924
commit da3135ac9b
6 changed files with 199 additions and 206 deletions
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26
rocket/src/main/scala/consts.scala
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@@ -21,10 +21,10 @@ trait ScalarOpConstants {
val PC_PCR = UInt(3, 2)
val A1_X = Bits("b??", 2)
val A1_RS1 = UInt(0, 2)
val A1_ZERO = UInt(1, 2)
val A1_PC = UInt(2, 2)
val A1_PCHI = UInt(3, 2)
val A1_ZERO = UInt(0, 2)
val A1_RS1 = UInt(1, 2)
val A1_PCHI = UInt(2, 2)
val A1_PC = UInt(3, 2)
val IMM_X = Bits("b???", 3)
val IMM_S = UInt(0, 3);
@@ -35,19 +35,21 @@ trait ScalarOpConstants {
val IMM_Z = UInt(5, 3);
val A2_X = Bits("b??", 2)
val A2_RS2 = UInt(0, 2)
val A2_IMM = UInt(1, 2)
val A2_ZERO = UInt(2, 3)
val A2_FOUR = UInt(3, 3)
val A2_ZERO = UInt(0, 2)
val A2_FOUR = UInt(1, 2)
val A2_RS2 = UInt(2, 2)
val A2_IMM = UInt(3, 2)
val X = Bool.DC
val N = Bool(false)
val Y = Bool(true)
val WB_X = UInt("b??", 2)
val WB_ALU = UInt(0, 3);
val WB_TSC = UInt(2, 3);
val WB_IRT = UInt(3, 3);
val NBYP = 4
val SZ_BYP = log2Up(NBYP)
val BYP_0 = 0
val BYP_EX = 1
val BYP_MEM = 2
val BYP_DC = 3
val SZ_DW = 1
val DW_X = X

92
rocket/src/main/scala/ctrl.scala
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@@ -11,8 +11,7 @@ class CtrlDpathIO extends Bundle()
// outputs to datapath
val sel_pc = UInt(OUTPUT, 3);
val killd = Bool(OUTPUT);
val ren2 = Bool(OUTPUT);
val ren1 = Bool(OUTPUT);
val ren = Vec.fill(2)(Bool(OUTPUT))
val sel_alu2 = UInt(OUTPUT, 3)
val sel_alu1 = UInt(OUTPUT, 2)
val sel_imm = UInt(OUTPUT, 3)
@@ -37,8 +36,9 @@ class CtrlDpathIO extends Bundle()
val ex_rs2_val = Bool(OUTPUT)
val ex_rocc_val = Bool(OUTPUT)
val mem_rocc_val = Bool(OUTPUT)
val mem_ll_bypass_rs1 = Bool(OUTPUT)
val mem_ll_bypass_rs2 = Bool(OUTPUT)
val bypass = Vec.fill(2)(Bool(OUTPUT))
val bypass_src = Vec.fill(2)(Bits(OUTPUT, SZ_BYP))
val ll_ready = Bool(OUTPUT)
// exception handling
val retire = Bool(OUTPUT)
val exception = Bool(OUTPUT);
@@ -50,11 +50,11 @@ class CtrlDpathIO extends Bundle()
val ex_br_type = Bits(OUTPUT, SZ_BR)
val ex_br_taken = Bool(INPUT)
val div_mul_rdy = Bool(INPUT)
val mem_ll_wb = Bool(INPUT)
val mem_ll_waddr = UInt(INPUT, 5)
val ex_waddr = UInt(INPUT, 5); // write addr from execute stage
val mem_waddr = UInt(INPUT, 5); // write addr from memory stage
val wb_waddr = UInt(INPUT, 5); // write addr from writeback stage
val ll_wen = Bool(INPUT)
val ll_waddr = UInt(INPUT, 5)
val ex_waddr = UInt(INPUT, 5)
val mem_waddr = UInt(INPUT, 5)
val wb_waddr = UInt(INPUT, 5)
val status = new Status().asInput
val fp_sboard_clr = Bool(INPUT);
val fp_sboard_clra = UInt(INPUT, 5);
@@ -543,9 +543,8 @@ class Control(implicit conf: RocketConfiguration) extends Module
(mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(11))))
val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen || mem_reg_rocc_val || mem_reg_csr != CSR.N)
val replay_mem = ll_wb_kill_mem || mem_reg_replay || fpu_kill_mem
val killm_common = ll_wb_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
val replay_mem = mem_reg_replay || fpu_kill_mem
val killm_common = take_pc_wb || mem_reg_xcpt || !mem_reg_valid
ctrl_killm := killm_common || mem_xcpt || fpu_kill_mem
wb_reg_replay := replay_mem && !take_pc_wb
@@ -577,23 +576,22 @@ class Control(implicit conf: RocketConfiguration) extends Module
wb_reg_rocc_val := mem_reg_rocc_val
}
val replay_wb = io.dmem.resp.bits.nack || wb_reg_replay ||
io.dpath.csr_replay || Bool(!conf.rocc.isEmpty) && wb_reg_rocc_val && !io.rocc.cmd.ready
val replay_wb_common =
io.dmem.resp.bits.nack || wb_reg_replay ||
io.dpath.ll_wen && wb_reg_wen || io.dpath.csr_replay
val wb_rocc_val = wb_reg_rocc_val && !replay_wb_common
val replay_wb = replay_wb_common || wb_reg_rocc_val && !io.rocc.cmd.ready
class Scoreboard(n: Int)
{
val r = Reg(init=Bits(0, n))
private var _next = r
private var cur = r
var ens = Bool(false)
def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
def clear(en: Bool, addr: UInt): Unit = {
val m = ~mask(en, addr)
update(en, _next & m)
//cur = cur & m
}
def read(addr: UInt) = r(addr)
def readBypassed(addr: UInt) = cur(addr)
def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))
def read(addr: UInt): Bool = r(addr)
def readBypassed(addr: UInt): Bool = _next(addr)
private val r = Reg(init=Bits(0, n))
private var _next = r
private var ens = Bool(false)
private def mask(en: Bool, addr: UInt) = Mux(en, UInt(1) << addr, UInt(0))
private def update(en: Bool, update: UInt) = {
_next = update
@@ -604,7 +602,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val sboard = new Scoreboard(32)
sboard.set((wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val) && io.dpath.wb_wen, io.dpath.wb_waddr)
sboard.clear(io.dpath.mem_ll_wb, io.dpath.mem_ll_waddr)
sboard.clear(io.dpath.ll_wen, io.dpath.ll_waddr)
val id_stall_fpu = if (conf.fpu) {
val fp_sboard = new Scoreboard(32)
@@ -613,10 +611,10 @@ class Control(implicit conf: RocketConfiguration) extends Module
fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
id_csr_en && !io.fpu.fcsr_rdy ||
io.fpu.dec.ren1 && fp_sboard.readBypassed(id_raddr1) ||
io.fpu.dec.ren2 && fp_sboard.readBypassed(id_raddr2) ||
io.fpu.dec.ren3 && fp_sboard.readBypassed(id_raddr3) ||
io.fpu.dec.wen && fp_sboard.readBypassed(id_waddr)
io.fpu.dec.ren1 && fp_sboard.read(id_raddr1) ||
io.fpu.dec.ren2 && fp_sboard.read(id_raddr2) ||
io.fpu.dec.ren3 && fp_sboard.read(id_raddr3) ||
io.fpu.dec.wen && fp_sboard.read(id_waddr)
} else Bool(false)
// write CAUSE CSR on an exception
@@ -638,6 +636,18 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.imem.req.bits.taken := !ex_reg_btb_hit || ex_reg_jalr
io.imem.req.valid := take_pc
val bypassDst = Array(id_raddr1, id_raddr2)
val bypassSrc = Array.fill(NBYP)((Bool(true), UInt(0)))
bypassSrc(BYP_EX) = (ex_reg_wen, io.dpath.ex_waddr)
bypassSrc(BYP_MEM) = (mem_reg_wen && !mem_reg_mem_val, io.dpath.mem_waddr)
bypassSrc(BYP_DC) = (mem_reg_wen, io.dpath.mem_waddr)
val doBypass = bypassDst.map(d => bypassSrc.map(s => s._1 && s._2 === d))
for (i <- 0 until io.dpath.bypass.size) {
io.dpath.bypass(i) := doBypass(i).reduce(_||_)
io.dpath.bypass_src(i) := PriorityEncoder(doBypass(i))
}
// stall for RAW/WAW hazards on PCRs, loads, AMOs, and mul/div in execute stage.
val data_hazard_ex = ex_reg_wen &&
(id_renx1.toBool && id_raddr1 === io.dpath.ex_waddr ||
@@ -669,24 +679,17 @@ class Control(implicit conf: RocketConfiguration) extends Module
id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem)
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
val data_hazard_wb = wb_reg_wen &&
(id_raddr1 != UInt(0) && id_renx1 && (id_raddr1 === io.dpath.wb_waddr) ||
id_raddr2 != UInt(0) && id_renx2 && (id_raddr2 === io.dpath.wb_waddr) ||
id_waddr != UInt(0) && id_wen && (id_waddr === io.dpath.wb_waddr))
val fp_data_hazard_wb = wb_reg_fp_wen &&
(io.fpu.dec.ren1 && id_raddr1 === io.dpath.wb_waddr ||
io.fpu.dec.ren2 && id_raddr2 === io.dpath.wb_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.wb_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.wb_waddr)
val id_wb_hazard = data_hazard_wb && (wb_dcache_miss || wb_reg_div_mul_val || wb_reg_rocc_val) ||
fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val)
val id_wb_hazard = fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val)
io.dpath.mem_ll_bypass_rs1 := io.dpath.mem_ll_wb && io.dpath.mem_ll_waddr === id_raddr1
io.dpath.mem_ll_bypass_rs2 := io.dpath.mem_ll_wb && io.dpath.mem_ll_waddr === id_raddr2
val id_sboard_hazard =
(id_raddr1 != UInt(0) && id_renx1 && sboard.read(id_raddr1) && !io.dpath.mem_ll_bypass_rs1 ||
id_raddr2 != UInt(0) && id_renx2 && sboard.read(id_raddr2) && !io.dpath.mem_ll_bypass_rs2 ||
id_waddr != UInt(0) && id_wen && sboard.read(id_waddr))
(id_raddr1 != UInt(0) && id_renx1 && sboard.readBypassed(id_raddr1) ||
id_raddr2 != UInt(0) && id_renx2 && sboard.readBypassed(id_raddr2) ||
id_waddr != UInt(0) && id_wen && sboard.readBypassed(id_waddr))
val ctrl_stalld =
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
@@ -702,8 +705,8 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen
io.dpath.wb_load := wb_reg_mem_val && wb_reg_wen
io.dpath.ren2 := id_renx2.toBool;
io.dpath.ren1 := id_renx1.toBool;
io.dpath.ren(1) := id_renx2
io.dpath.ren(0) := id_renx1
io.dpath.sel_alu2 := id_sel_alu2.toUInt
io.dpath.sel_alu1 := id_sel_alu1.toUInt
io.dpath.sel_imm := id_sel_imm.toUInt
@@ -717,6 +720,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.dpath.ex_predicted_taken := ex_reg_btb_hit
io.dpath.ex_wen := ex_reg_wen;
io.dpath.mem_wen := mem_reg_wen;
io.dpath.ll_ready := !wb_reg_wen
io.dpath.wb_wen := wb_reg_wen && !replay_wb
io.dpath.retire := wb_reg_valid && !replay_wb
io.dpath.csr := wb_reg_csr
@@ -737,5 +741,5 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.dmem.req.bits.typ := ex_reg_mem_type
io.dmem.req.bits.phys := Bool(false)
io.rocc.cmd.valid := wb_reg_rocc_val
io.rocc.cmd.valid := wb_rocc_val
}

210
rocket/src/main/scala/dpath.scala
View File

@@ -27,12 +27,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val ex_reg_sel_alu1 = Reg(UInt())
val ex_reg_sel_imm = Reg(UInt())
val ex_reg_kill = Reg(Bool())
val ex_reg_rs1_bypass = Reg(Bool())
val ex_reg_rs1_lsb = Reg(Bits())
val ex_reg_rs1_msb = Reg(Bits())
val ex_reg_rs2_bypass = Reg(Bool())
val ex_reg_rs2_lsb = Reg(Bits())
val ex_reg_rs2_msb = Reg(Bits())
val ex_reg_rs_bypass = Vec.fill(2)(Reg(Bool()))
val ex_reg_rs_lsb = Vec.fill(2)(Reg(Bits()))
val ex_reg_rs_msb = Vec.fill(2)(Reg(Bits()))
// memory definitions
val mem_reg_pc = Reg(UInt())
@@ -44,38 +41,38 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
// writeback definitions
val wb_reg_pc = Reg(UInt())
val wb_reg_inst = Reg(Bits())
val wb_reg_waddr = Reg(UInt())
val wb_reg_wdata = Reg(Bits())
val wb_reg_ll_wb = Reg(init=Bool(false))
val wb_wdata = Bits()
val wb_reg_rs2 = Reg(Bits())
val wb_wen = io.ctrl.wb_wen || wb_reg_ll_wb
// instruction decode stage
val id_inst = io.imem.resp.bits.data
val id_pc = io.imem.resp.bits.pc
val regfile_ = Mem(Bits(width = 64), 31)
def readRF(a: UInt) = regfile_(~a)
def writeRF(a: UInt, d: Bits) = regfile_(~a) := d
class RegFile {
private val rf = Mem(UInt(width = 64), 31)
private val reads = collection.mutable.ArrayBuffer[(UInt,UInt)]()
private var canRead = true
def read(addr: UInt) = {
require(canRead)
reads += addr -> UInt()
reads.last._2 := rf(~addr)
reads.last._2
}
def write(addr: UInt, data: UInt) = {
canRead = false
when (addr != UInt(0)) {
rf(~addr) := data
for ((raddr, rdata) <- reads)
when (addr === raddr) { rdata := data }
}
}
}
val rf = new RegFile
val id_raddr1 = id_inst(19,15).toUInt;
val id_raddr2 = id_inst(24,20).toUInt;
// bypass muxes
val id_rs1_zero = id_raddr1 === UInt(0)
val id_rs1_ex_bypass = io.ctrl.ex_wen && id_raddr1 === io.ctrl.ex_waddr
val id_rs1_mem_bypass = io.ctrl.mem_wen && id_raddr1 === io.ctrl.mem_waddr
val id_rs1_bypass = id_rs1_zero || id_rs1_ex_bypass || id_rs1_mem_bypass || io.ctrl.mem_ll_bypass_rs1
val id_rs1_bypass_src = Mux(id_rs1_zero, UInt(0), Mux(id_rs1_ex_bypass, UInt(1), Mux(io.ctrl.mem_load, UInt(3), UInt(2))))
val id_rs1 = Mux(wb_wen && id_raddr1 === wb_reg_waddr, wb_wdata, readRF(id_raddr1))
val id_rs2_zero = id_raddr2 === UInt(0)
val id_rs2_ex_bypass = io.ctrl.ex_wen && id_raddr2 === io.ctrl.ex_waddr
val id_rs2_mem_bypass = io.ctrl.mem_wen && id_raddr2 === io.ctrl.mem_waddr
val id_rs2_bypass = id_rs2_zero || id_rs2_ex_bypass || id_rs2_mem_bypass || io.ctrl.mem_ll_bypass_rs2
val id_rs2_bypass_src = Mux(id_rs2_zero, UInt(0), Mux(id_rs2_ex_bypass, UInt(1), Mux(io.ctrl.mem_load, UInt(3), UInt(2))))
val id_rs2 = Mux(wb_wen && id_raddr2 === wb_reg_waddr, wb_wdata, readRF(id_raddr2))
// RF read ports + bypass from WB stage
val id_raddr = Vec(id_inst(19,15), id_inst(24,20))
val id_rs = id_raddr.map(rf.read _)
// immediate generation
def imm(sel: Bits, inst: Bits) = {
@@ -109,56 +106,49 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
ex_reg_sel_alu2 := io.ctrl.sel_alu2
ex_reg_sel_alu1 := io.ctrl.sel_alu1
ex_reg_sel_imm := io.ctrl.sel_imm
ex_reg_rs1_bypass := id_rs1_bypass && io.ctrl.ren1
ex_reg_rs2_bypass := id_rs2_bypass && io.ctrl.ren2
when (io.ctrl.ren1) {
ex_reg_rs1_lsb := id_rs1_bypass_src
when (!id_rs1_bypass) {
ex_reg_rs1_lsb := id_rs1(id_rs1_bypass_src.getWidth-1,0)
ex_reg_rs1_msb := id_rs1(63,id_rs1_bypass_src.getWidth)
}
}
when (io.ctrl.ren2) {
ex_reg_rs2_lsb := id_rs2_bypass_src
when (!id_rs2_bypass) {
ex_reg_rs2_lsb := id_rs2(id_rs2_bypass_src.getWidth-1,0)
ex_reg_rs2_msb := id_rs2(63,id_rs2_bypass_src.getWidth)
ex_reg_rs_bypass := io.ctrl.bypass
for (i <- 0 until id_rs.size) {
when (io.ctrl.ren(i)) {
ex_reg_rs_lsb(i) := id_rs(i)(SZ_BYP-1,0)
when (!io.ctrl.bypass(i)) {
ex_reg_rs_msb(i) := id_rs(i) >> SZ_BYP
}
}
when (io.ctrl.bypass(i)) { ex_reg_rs_lsb(i) := io.ctrl.bypass_src(i) }
}
}
val ex_raddr1 = ex_reg_inst(19,15)
val ex_raddr2 = ex_reg_inst(24,20)
val dmem_resp_data = if (conf.fastLoadByte) io.dmem.resp.bits.data_subword else io.dmem.resp.bits.data
val ex_rs1 =
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(3) && Bool(conf.fastLoadWord), dmem_resp_data,
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(2), wb_reg_wdata,
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(1), mem_reg_wdata,
Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UInt(0), Bits(0),
Mux(AVec(A1_ZERO, A1_PCHI) contains ex_reg_sel_alu1, Bits(0),
Cat(ex_reg_rs1_msb, ex_reg_rs1_lsb))))))
val ex_rs2 =
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(3) && Bool(conf.fastLoadWord), dmem_resp_data,
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(2), wb_reg_wdata,
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(1), mem_reg_wdata,
Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UInt(0), Bits(0),
Cat(ex_reg_rs2_msb, ex_reg_rs2_lsb)))))
val bypass = Vec.fill(NBYP)(Bits())
bypass(BYP_0) := Bits(0)
bypass(BYP_EX) := mem_reg_wdata
bypass(BYP_MEM) := wb_reg_wdata
bypass(BYP_DC) := (if (conf.fastLoadByte) io.dmem.resp.bits.data_subword
else if (conf.fastLoadWord) io.dmem.resp.bits.data
else wb_reg_wdata)
val ex_rs = for (i <- 0 until id_rs.size)
yield Mux(ex_reg_rs_bypass(i), bypass(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
val ex_imm = imm(ex_reg_sel_imm, ex_reg_inst)
val ex_op1_hi = Mux(AVec(A1_PC, A1_PCHI) contains ex_reg_sel_alu1, ex_reg_pc >> 12, ex_rs1 >> 12).toSInt
val ex_op1_lo = Mux(ex_reg_sel_alu1 === A1_PC, ex_reg_pc(11,0), ex_rs1(11,0)).toSInt
val ex_op1_hi = MuxLookup(ex_reg_sel_alu1, ex_reg_pc.toSInt >> 12, Seq(
A1_RS1 -> (ex_rs(0).toSInt >> 12),
A1_ZERO -> SInt(0)))
val ex_op1_lo = MuxLookup(ex_reg_sel_alu1, UInt(0), Seq(
A1_RS1 -> ex_rs(0)(11,0),
A1_PC -> ex_reg_pc(11,0)))
val ex_op1 = Cat(ex_op1_hi, ex_op1_lo)
val ex_op2 = Mux(ex_reg_sel_alu2 === A2_RS2, ex_rs2.toSInt,
Mux(ex_reg_sel_alu2 === A2_IMM, ex_imm,
Mux(ex_reg_sel_alu2 === A2_ZERO, SInt(0),
SInt(4))))
val ex_op2 = MuxLookup(ex_reg_sel_alu2, SInt(0), Seq(
A2_RS2 -> ex_rs(1).toSInt,
A2_IMM -> ex_imm,
A2_FOUR -> SInt(4)))
val alu = Module(new ALU)
alu.io.dw := ex_reg_ctrl_fn_dw;
alu.io.fn := ex_reg_ctrl_fn_alu;
alu.io.in2 := ex_op2.toUInt
alu.io.in1 := ex_op1.toUInt
alu.io.in1 := ex_op1
// multiplier and divider
val div = Module(new MulDiv(mulUnroll = if (conf.fastMulDiv) 8 else 1,
@@ -166,15 +156,13 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
div.io.req.valid := io.ctrl.div_mul_val
div.io.req.bits.dw := ex_reg_ctrl_fn_dw
div.io.req.bits.fn := ex_reg_ctrl_fn_alu
div.io.req.bits.in1 := ex_rs1
div.io.req.bits.in2 := ex_rs2
div.io.req.bits.in1 := ex_rs(0)
div.io.req.bits.in2 := ex_rs(1)
div.io.req.bits.tag := io.ctrl.ex_waddr
div.io.kill := io.ctrl.div_mul_kill
div.io.resp.ready := !io.ctrl.mem_wen
io.ctrl.div_mul_rdy := div.io.req.ready
io.fpu.fromint_data := ex_rs1
io.ctrl.ex_waddr := ex_reg_inst(11,7)
io.fpu.fromint_data := ex_rs(0)
def vaSign(a0: UInt, ea: Bits) = {
// efficient means to compress 64-bit VA into VADDR_BITS+1 bits
@@ -185,16 +173,15 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
Mux(a === SInt(-1) || a === SInt(-2), e === SInt(-1),
e(0)))
}
val ex_br_base = Mux(io.ctrl.ex_jalr, ex_rs1, ex_reg_pc)
val ex_br_base = Mux(io.ctrl.ex_jalr, ex_rs(0), ex_reg_pc)
val ex_br_offset = Mux(io.ctrl.ex_predicted_taken, SInt(4), ex_imm(19,0).toSInt)
val ex_br64 = ex_br_base + ex_br_offset
val ex_br_msb = Mux(io.ctrl.ex_jalr, vaSign(ex_rs1, ex_br64), vaSign(ex_reg_pc, ex_br64))
val ex_br_msb = Mux(io.ctrl.ex_jalr, vaSign(ex_rs(0), ex_br64), vaSign(ex_reg_pc, ex_br64))
val ex_br_addr = Cat(ex_br_msb, ex_br64(VADDR_BITS-1,0))
// D$ request interface (registered inside D$ module)
// other signals (req_val, req_rdy) connect to control module
io.dmem.req.bits.addr := Cat(vaSign(ex_rs1, alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt
io.dmem.req.bits.data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(VADDR_BITS-1,0)).toUInt
io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
require(io.dmem.req.bits.tag.getWidth >= 6)
@@ -212,14 +199,14 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
io.ptw.status := pcr.io.status
// branch resolution logic
io.ctrl.jalr_eq := ex_rs1 === id_pc.toSInt && ex_reg_inst(31,20) === UInt(0)
io.ctrl.jalr_eq := ex_rs(0) === id_pc.toSInt && ex_reg_inst(31,20) === UInt(0)
io.ctrl.ex_br_taken :=
Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs1 === ex_rs2,
Mux(io.ctrl.ex_br_type === BR_NE, ex_rs1 != ex_rs2,
Mux(io.ctrl.ex_br_type === BR_LT, ex_rs1.toSInt < ex_rs2.toSInt,
Mux(io.ctrl.ex_br_type === BR_GE, ex_rs1.toSInt >= ex_rs2.toSInt,
Mux(io.ctrl.ex_br_type === BR_LTU, ex_rs1 < ex_rs2,
Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2,
Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs(0) === ex_rs(1),
Mux(io.ctrl.ex_br_type === BR_NE, ex_rs(0) != ex_rs(1),
Mux(io.ctrl.ex_br_type === BR_LT, ex_rs(0).toSInt < ex_rs(1).toSInt,
Mux(io.ctrl.ex_br_type === BR_GE, ex_rs(0).toSInt >= ex_rs(1).toSInt,
Mux(io.ctrl.ex_br_type === BR_LTU, ex_rs(0) < ex_rs(1),
Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs(0) >= ex_rs(1),
io.ctrl.ex_br_type === BR_J))))))
// memory stage
@@ -228,13 +215,12 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
mem_reg_pc := ex_reg_pc
mem_reg_inst := ex_reg_inst
mem_reg_wdata := alu.io.out
when (io.ctrl.ex_rs2_val) {
mem_reg_rs2 := ex_rs2
}
}
// for load/use hazard detection (load byte/halfword)
io.ctrl.mem_waddr := mem_reg_inst(11,7)
when (io.ctrl.ex_rs2_val) {
mem_reg_rs2 := ex_rs(1)
}
io.dmem.req.bits.data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
// writeback arbitration
val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
@@ -243,28 +229,27 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
val dmem_resp_replay = io.dmem.resp.bits.replay && io.dmem.resp.bits.has_data
val mem_ll_wdata = Bits()
mem_ll_wdata := div.io.resp.bits.data
io.ctrl.mem_ll_waddr := div.io.resp.bits.tag
io.ctrl.mem_ll_wb := div.io.resp.valid && !io.ctrl.mem_wen
val ll_wdata = Bits()
div.io.resp.ready := io.ctrl.ll_ready
ll_wdata := div.io.resp.bits.data
io.ctrl.ll_waddr := div.io.resp.bits.tag
io.ctrl.ll_wen := div.io.resp.fire()
if (!conf.rocc.isEmpty) {
io.rocc.resp.ready := !io.ctrl.mem_wen && !io.ctrl.mem_rocc_val
io.rocc.resp.ready := io.ctrl.ll_ready
when (io.rocc.resp.fire()) {
div.io.resp.ready := Bool(false)
mem_ll_wdata := io.rocc.resp.bits.data
io.ctrl.mem_ll_waddr := io.rocc.resp.bits.rd
io.ctrl.mem_ll_wb := Bool(true)
ll_wdata := io.rocc.resp.bits.data
io.ctrl.ll_waddr := io.rocc.resp.bits.rd
io.ctrl.ll_wen := Bool(true)
}
}
when (dmem_resp_replay && dmem_resp_xpu) {
div.io.resp.ready := Bool(false)
if (!conf.rocc.isEmpty)
io.rocc.resp.ready := Bool(false)
mem_ll_wdata := io.dmem.resp.bits.data_subword
io.ctrl.mem_ll_waddr := dmem_resp_waddr
io.ctrl.mem_ll_wb := Bool(true)
io.ctrl.ll_waddr := dmem_resp_waddr
io.ctrl.ll_wen := Bool(true)
}
when (io.ctrl.mem_ll_waddr === UInt(0)) { io.ctrl.mem_ll_wb := Bool(false) }
io.fpu.dmem_resp_val := dmem_resp_valid && dmem_resp_fpu
io.fpu.dmem_resp_data := io.dmem.resp.bits.data
@@ -274,24 +259,20 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
// writeback stage
when (!mem_reg_kill) {
wb_reg_pc := mem_reg_pc
wb_reg_waddr := io.ctrl.mem_waddr
wb_reg_inst := mem_reg_inst
wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata)
}
when (io.ctrl.mem_rocc_val) {
wb_reg_rs2 := mem_reg_rs2
}
wb_reg_ll_wb := io.ctrl.mem_ll_wb
when (io.ctrl.mem_ll_wb) {
wb_reg_waddr := io.ctrl.mem_ll_waddr
wb_reg_wdata := mem_ll_wdata
}
wb_wdata := Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword,
wb_wdata := Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data_subword,
Mux(io.ctrl.ll_wen, ll_wdata,
Mux(io.ctrl.csr != CSR.N, pcr.io.rw.rdata,
wb_reg_wdata))
wb_reg_wdata)))
when (wb_wen) { writeRF(wb_reg_waddr, wb_wdata) }
io.ctrl.wb_waddr := wb_reg_waddr
val wb_wen = io.ctrl.ll_wen || io.ctrl.wb_wen
val wb_waddr = Mux(io.ctrl.ll_wen, io.ctrl.ll_waddr, io.ctrl.wb_waddr)
when (wb_wen) { rf.write(wb_waddr, wb_wdata) }
// scoreboard clear (for div/mul and D$ load miss writebacks)
io.ctrl.fp_sboard_clr := dmem_resp_replay && dmem_resp_fpu
@@ -312,11 +293,16 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
Mux(io.ctrl.sel_pc === PC_EX, ex_br_addr,
Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec,
wb_reg_pc)).toUInt // PC_WB
// for hazard/bypass opportunity detection
io.ctrl.ex_waddr := ex_reg_inst(11,7)
io.ctrl.mem_waddr := mem_reg_inst(11,7)
io.ctrl.wb_waddr := wb_reg_inst(11,7)
printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
pcr.io.time(32,0), io.ctrl.retire, wb_reg_pc,
Mux(wb_wen, wb_reg_waddr, UInt(0)), wb_wdata,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs1)),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs2)),
Mux(wb_wen, wb_waddr, UInt(0)), wb_wdata,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
wb_reg_inst, wb_reg_inst)
}

2
rocket/src/main/scala/dpath_util.scala
View File

@@ -267,7 +267,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt }
when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false); }
when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0)) { reg_tohost := wdata } }
when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } }
when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) }
when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata; }
when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata; }

74
rocket/src/main/scala/instructions.scala
View File

@@ -186,60 +186,60 @@ object Instructions {
def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
}
object CSRs {
val sup0 = 1280
val fflags = 1
val frm = 2
val fcsr = 3
val cycle = 4
val time = 5
val instret = 6
val sup1 = 1281
val evec = 1288
val cause = 1289
val status = 1290
val hartid = 1291
val impl = 1292
val epc = 1282
val send_ipi = 1294
val clear_ipi = 1295
val badvaddr = 1283
val ptbr = 1284
val stats = 1308
val reset = 1309
val tohost = 1310
val asid = 1285
val count = 1286
val compare = 1287
val fromhost = 1311
val fatc = 1293
val fflags = 0x1
val frm = 0x2
val fcsr = 0x3
val sup0 = 0x500
val sup1 = 0x501
val epc = 0x502
val badvaddr = 0x503
val ptbr = 0x504
val asid = 0x505
val count = 0x506
val compare = 0x507
val evec = 0x508
val cause = 0x509
val status = 0x50a
val hartid = 0x50b
val impl = 0x50c
val fatc = 0x50d
val send_ipi = 0x50e
val clear_ipi = 0x50f
val stats = 0x51c
val reset = 0x51d
val tohost = 0x51e
val fromhost = 0x51f
val cycle = 0xc00
val time = 0xc01
val instret = 0xc02
val all = {
val res = collection.mutable.ArrayBuffer[Int]()
res += sup0
res += fflags
res += frm
res += fcsr
res += cycle
res += time
res += instret
res += sup0
res += sup1
res += epc
res += badvaddr
res += ptbr
res += asid
res += count
res += compare
res += evec
res += cause
res += status
res += hartid
res += impl
res += epc
res += fatc
res += send_ipi
res += clear_ipi
res += badvaddr
res += ptbr
res += stats
res += reset
res += tohost
res += asid
res += count
res += compare
res += fromhost
res += fatc
res += cycle
res += time
res += instret
res.toArray
}
}

1
rocket/src/main/scala/util.scala
View File

@@ -9,6 +9,7 @@ object Util
implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false
implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0
implicit def booleanToBool(x: Boolean): Bits = Bool(x)
implicit def intSeqToUIntSeq(x: Iterable[Int]): Iterable[UInt] = x.map(UInt(_))
implicit def wcToUInt(c: WideCounter): UInt = c.value
}