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Tl2 addr width0 (#346)

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* tilelink2 Edges: add accessor methods for address and addr_{hi,lo}

* tilelink2: use addr_lo instead of relying on truncation

Truncation can mess up if the width should be 0, but IS 1.
This commit is contained in:
Wesley W. Terpstra
2016-09-26 17:00:03 -07:00
committed by GitHub
parent 72c205b54f
commit d9e209365d
2 changed files with 63 additions and 50 deletions
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11
src/main/scala/uncore/tilelink2/WidthWidget.scala
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@ -32,11 +32,12 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
val mask = Cat(edgeIn.mask(in.bits), rmask)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val addr_lo = in.bits match {
val addr_all = in.bits match {
case x: TLAddrChannel => edgeIn.address(x)
case _ => UInt(0)
}
val addr = addr_lo >> log2Ceil(outBytes)
val addr_hi = edgeOut.addr_hi(addr_all)
val addr_lo = edgeOut.addr_lo(addr_all)
val count = RegInit(UInt(0, width = log2Ceil(ratio)))
val first = count === UInt(0)
@ -72,9 +73,9 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
edgeOut.data(out.bits) := dataOut
out.bits match {
case a: TLBundleA => a.addr_hi := addr; a.mask := maskOut
case b: TLBundleB => b.addr_hi := addr; b.mask := maskOut
case c: TLBundleC => c.addr_hi := addr; c.addr_lo := addr_lo
case a: TLBundleA => a.addr_hi := addr_hi; a.mask := maskOut
case b: TLBundleB => b.addr_hi := addr_hi; b.mask := maskOut
case c: TLBundleC => c.addr_hi := addr_hi; c.addr_lo := addr_lo
case d: TLBundleD => ()
// addr_lo gets padded with 0s on D channel, the only lossy transform in this core
// this should be safe, because we only care about addr_log on D to determine which