riscv/rocket-chip
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Moved RenEn to ChiselUtil

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This commit is contained in:
Henry Cook 2013-08-12 22:18:25 -07:00
parent 1a9e43aa11
commit d9b3c7cfc8
1 changed files with 0 additions and 14 deletions
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14
rocket/src/main/scala/fpu.scala
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@ -176,20 +176,6 @@ class CtrlFPUIO extends Bundle {
val sboard_clra = UInt(INPUT, 5) val sboard_clra = UInt(INPUT, 5)
} }
object RegEn
{
def apply[T <: Data](data: T, en: Bool) = {
val r = Reg(data)
when (en) { r := data }
r
}
def apply[T <: Bits](data: T, en: Bool, resetVal: T) = {
val r = RegReset(resetVal)
when (en) { r := data }
r
}
}
class FPToInt extends Module class FPToInt extends Module
{ {
class Input extends Bundle { class Input extends Bundle {