From d9a203b0f0064f542677a4dda2792c8c11104502 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Tue, 22 Nov 2016 18:38:55 -0800
Subject: [PATCH] PositionalMultiQueue: convert 'next' to a single write port

---
 src/main/scala/util/PositionalMultiQueue.scala | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/util/PositionalMultiQueue.scala b/src/main/scala/util/PositionalMultiQueue.scala
index cd87ebdc..eadb1f88 100644
--- a/src/main/scala/util/PositionalMultiQueue.scala
+++ b/src/main/scala/util/PositionalMultiQueue.scala
@@ -45,6 +45,10 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T],
     // ensure the user never stores to the same position twice
     assert (!guard(io.enq.bits.pos))
     guard(io.enq.bits.pos) := Bool(true)
+
+    when (!empty(io.enq.bits.way)) {
+      next(tail(io.enq.bits.way)) := io.enq.bits.pos
+    }
   }
 
   val deq = Wire(io.deq)
@@ -59,8 +63,6 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T],
       tail(i) := io.enq.bits.pos
       when (empty(i)) {
         head(i) := io.enq.bits.pos
-      } .otherwise {
-        next(tail(i)) := io.enq.bits.pos
       }
     }