From d93677a343215b5391fb45678eda73b1adbd78e8 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 25 Apr 2016 17:55:22 -0700 Subject: [PATCH] Support larger cache sets when not using VM --- rocket/src/main/scala/nbdcache.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index ade7ed85..bc006ed8 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -25,7 +25,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters { val idxLSB = blockOffBits val offsetmsb = idxLSB-1 val offsetlsb = wordOffBits - val rowWords = rowBits/wordBits + val rowWords = rowBits/wordBits val doNarrowRead = coreDataBits * nWays % rowBits == 0 val encDataBits = code.width(coreDataBits) val encRowBits = encDataBits*rowWords @@ -37,7 +37,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters { require(lrscCycles >= 32) // ISA requires 16-insn LRSC sequences to succeed require(isPow2(nSets)) require(rowBits <= outerDataBits) - require(untagBits <= pgIdxBits) + require(!usingVM || untagBits <= pgIdxBits) } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module @@ -800,7 +800,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) { val dtlb = Module(new TLB) io.ptw <> dtlb.io.ptw - dtlb.io.req.valid := s1_valid_masked && s1_readwrite && !s1_req.phys + dtlb.io.req.valid := s1_valid_masked && s1_readwrite dtlb.io.req.bits.passthrough := s1_req.phys dtlb.io.req.bits.asid := UInt(0) dtlb.io.req.bits.vpn := s1_req.addr >> pgIdxBits @@ -866,7 +866,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) { writeArb.io.out.ready := data.io.write.ready data.io.write.bits := writeArb.io.out.bits val wdata_encoded = (0 until rowWords).map(i => code.encode(writeArb.io.out.bits.data(coreDataBits*(i+1)-1,coreDataBits*i))) - data.io.write.bits.data := Vec(wdata_encoded).toBits + data.io.write.bits.data := Cat(wdata_encoded.reverse) // tag read for new requests metaReadArb.io.in(4).valid := io.cpu.req.valid