riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Empty commit to force travis

Browse Source
This commit is contained in:
Megan Wachs 2017-05-16 22:56:58 -07:00 committed by GitHub
parent 5f22e91a7f
commit d8996ea85f
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/main/scala/coreplex/Configs.scala
View File

@ -226,3 +226,4 @@ class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, he
class WithRationalRocketTiles extends Config((site, here, up) => {
case RocketCrossing => RationalCrossing()
})