Chisel3 bulk connect non-commutativity

junctions/src/main/scala/memserdes.scala

@@ -248,7 +248,7 @@ class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module
   val io = new QueueIO(data, entries)
 
   val fq = Module(new HellaFlowQueue(entries)(data))
-  io.enq <> fq.io.enq
+  fq.io.enq <> io.enq
   io.deq <> Queue(fq.io.deq, 1, pipe = true)
 }
 
@@ -303,7 +303,7 @@ class MemIOArbiter(val arbN: Int) extends MIFModule {
       io.inner(i).resp.bits := io.outer.resp.bits
       io.inner(i).resp.bits.tag := io.outer.resp.bits.tag >> UInt(log2Up(arbN))
     }
-  } else { io.inner.head <> io.outer }
+  } else { io.outer <> io.inner.head }
 }
 
 object MemIOMemPipeIOConverter {

junctions/src/main/scala/slowio.scala

@@ -51,7 +51,7 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
   val fromhost_q = Module(new Queue(data,1))
   fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || this.reset)
   fromhost_q.io.enq.bits := io.in_slow.bits
-  fromhost_q.io.deq <> io.in_fast
+  io.in_fast <> fromhost_q.io.deq
 
   val tohost_q = Module(new Queue(data,1))
   tohost_q.io.enq <> io.out_fast