riscv/rocket-chip
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Chisel3 bulk connect non-commutativity

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This commit is contained in:
Andrew Waterman 2015-08-03 19:47:16 -07:00
parent eb57433f43
commit d85c46bc60
2 changed files with 3 additions and 3 deletions
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4
junctions/src/main/scala/memserdes.scala
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@ -248,7 +248,7 @@ class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module
val io = new QueueIO(data, entries) val io = new QueueIO(data, entries)
val fq = Module(new HellaFlowQueue(entries)(data)) val fq = Module(new HellaFlowQueue(entries)(data))
io.enq <> fq.io.enq fq.io.enq <> io.enq
io.deq <> Queue(fq.io.deq, 1, pipe = true) io.deq <> Queue(fq.io.deq, 1, pipe = true)
} }
@ -303,7 +303,7 @@ class MemIOArbiter(val arbN: Int) extends MIFModule {
io.inner(i).resp.bits := io.outer.resp.bits io.inner(i).resp.bits := io.outer.resp.bits
io.inner(i).resp.bits.tag := io.outer.resp.bits.tag >> UInt(log2Up(arbN)) io.inner(i).resp.bits.tag := io.outer.resp.bits.tag >> UInt(log2Up(arbN))
} }
} else { io.inner.head <> io.outer } } else { io.outer <> io.inner.head }
} }
object MemIOMemPipeIOConverter { object MemIOMemPipeIOConverter {

2
junctions/src/main/scala/slowio.scala
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@ -51,7 +51,7 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
val fromhost_q = Module(new Queue(data,1)) val fromhost_q = Module(new Queue(data,1))
fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || this.reset) fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || this.reset)
fromhost_q.io.enq.bits := io.in_slow.bits fromhost_q.io.enq.bits := io.in_slow.bits
fromhost_q.io.deq <> io.in_fast io.in_fast <> fromhost_q.io.deq
val tohost_q = Module(new Queue(data,1)) val tohost_q = Module(new Queue(data,1))
tohost_q.io.enq <> io.out_fast tohost_q.io.enq <> io.out_fast