diff --git a/uncore/src/coherence.scala b/uncore/src/coherence.scala
index 03c5c8f1..b869436a 100644
--- a/uncore/src/coherence.scala
+++ b/uncore/src/coherence.scala
@@ -1,7 +1,5 @@
 package uncore
-
 import Chisel._
-import Constants._
 
 abstract trait CoherenceAgentRole
 abstract trait ClientCoherenceAgent extends CoherenceAgentRole
diff --git a/uncore/src/consts.scala b/uncore/src/consts.scala
index aaa7b7a8..4e3c814e 100644
--- a/uncore/src/consts.scala
+++ b/uncore/src/consts.scala
@@ -36,6 +36,7 @@ trait TileLinkSizeConstants extends
   val ACQUIRE_ATOMIC_OP_BITS = 4
 }
 
+object MemoryOpConstants extends MemoryOpConstants
 trait MemoryOpConstants {
   val MT_X  = Bits("b???", 3);
   val MT_B  = Bits("b000", 3);
@@ -82,6 +83,7 @@ trait MemoryInterfaceConstants extends
   val REFILL_CYCLES = CACHE_DATA_SIZE_IN_BYTES*8/MEM_DATA_BITS
 }
 
+object AddressConstants extends AddressConstants
 trait AddressConstants { 
   val PADDR_BITS = 32
   val VADDR_BITS = 43;
diff --git a/uncore/src/llc.scala b/uncore/src/llc.scala
index 1f9f4b2a..6b0c77f2 100644
--- a/uncore/src/llc.scala
+++ b/uncore/src/llc.scala
@@ -1,8 +1,5 @@
 package uncore
-
 import Chisel._
-import Node._
-import Constants._
 
 class BigMem[T <: Data](n: Int, preLatency: Int, postLatency: Int, leaf: Mem[Bits])(gen: => T) extends Component
 {
diff --git a/uncore/src/memserdes.scala b/uncore/src/memserdes.scala
index 88a6f1b3..c7c8e773 100644
--- a/uncore/src/memserdes.scala
+++ b/uncore/src/memserdes.scala
@@ -1,8 +1,5 @@
 package uncore
-
 import Chisel._
-import Node._
-import Constants._
 import scala.math._
 
 class ioMemSerialized(w: Int) extends Bundle
diff --git a/uncore/src/network.scala b/uncore/src/network.scala
new file mode 100644
index 00000000..cdaa8118
--- /dev/null
+++ b/uncore/src/network.scala
@@ -0,0 +1,193 @@
+package uncore
+import Chisel._
+import scala.collection.mutable.Stack
+
+class PairedDataIO[M <: Data, D <: Data]()(m: => M, d: => D) extends Bundle {
+  val meta = new FIFOIO()(m)
+  val data = new FIFOIO()(d)
+  override def clone = { new PairedDataIO()(m,d).asInstanceOf[this.type] }
+}
+
+class PairedArbiterIO[M <: Data, D <: Data](n: Int)(m: => M, d: => D) extends Bundle {
+  val in  = Vec(n) { new PairedDataIO()(m,d) }.flip
+  val out = new PairedDataIO()(m,d)  
+  val meta_chosen = Bits(OUTPUT, log2Up(n)) 
+  val data_chosen = Bits(OUTPUT, log2Up(n)) 
+  override def clone = { new PairedArbiterIO(n)(m,d).asInstanceOf[this.type] }
+}
+
+class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock: Option[M => Bool] = None)(meta: => M, data: => D) extends Component {
+  require(isPow2(count))
+  val io = new PairedArbiterIO(n)(meta,data)
+  val locked  = if(count > 1) Reg(resetVal = Bool(false)) else Bool(false)
+  val lockIdx = if(count > 1) Reg(resetVal = UFix(n-1)) else UFix(n-1)
+  val grant = List.fill(n)(Bool())
+  val meta_chosen = Bits(width = log2Up(n))
+
+  val chosen_meta_has_data = needsLock.map(_(io.in(meta_chosen).meta.bits)).getOrElse(Bool(true))
+  val valid_meta_has_data = io.in(meta_chosen).meta.valid && chosen_meta_has_data
+  val grant_chosen_meta = !(locked && chosen_meta_has_data)
+  (0 until n).map(i => io.in(i).meta.ready := grant(i) && grant_chosen_meta && io.out.meta.ready)
+  (0 until n).map(i => io.in(i).data.ready := Mux(locked, lockIdx === UFix(i), grant(i) && valid_meta_has_data) && io.out.data.ready)
+  io.out.meta.valid := io.in(meta_chosen).meta.valid && grant_chosen_meta
+  io.out.data.valid := Mux(locked, io.in(lockIdx).data.valid, io.in(meta_chosen).data.valid && valid_meta_has_data)
+  io.out.meta.bits := io.in(meta_chosen).meta.bits
+  io.out.data.bits := Mux(locked, io.in(lockIdx).data.bits, io.in(meta_chosen).data.bits)
+  io.meta_chosen := meta_chosen
+  io.data_chosen := Mux(locked, lockIdx, meta_chosen)
+
+  if(count > 1){
+    val cnt = Reg(resetVal = UFix(0, width = log2Up(count)))
+    val cnt_next = cnt + UFix(1)
+    when(io.out.data.fire()){
+      cnt := cnt_next
+      when(cnt_next === UFix(0)) {
+        locked := Bool(false)
+      }
+    }
+    when(io.out.meta.fire()) {
+      when(needsLock.map(_(io.out.meta.bits)).getOrElse(Bool(true))) {
+        when(!locked) {
+          locked := Bool(true)
+          lockIdx := Vec(io.in.map{in => in.meta.fire()}){Bool()}.indexWhere{i: Bool => i} 
+        }
+      }
+    }
+  }
+  val last_grant = Reg(resetVal = Bits(0, log2Up(n)))
+  val ctrl = ArbiterCtrl((0 until n).map(i => io.in(i).meta.valid && UFix(i) > last_grant) ++ io.in.map(_.meta.valid))
+  (0 until n).map(i => grant(i) := ctrl(i) && UFix(i) > last_grant || ctrl(i + n))
+
+  var choose = Bits(n-1)
+  for (i <- n-2 to 0 by -1)
+    choose = Mux(io.in(i).meta.valid, Bits(i), choose)
+  for (i <- n-1 to 1 by -1)
+    choose = Mux(io.in(i).meta.valid && UFix(i) > last_grant, Bits(i), choose)
+  meta_chosen := choose
+
+  when (io.out.meta.fire()) { last_grant := meta_chosen }
+}
+
+class PairedCrossbar[M <: Data, D <: Data](count: Int, needsLock: Option[PhysicalNetworkIO[M] => Bool] = None)(meta: => M, data: => D)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
+  val io = new Bundle {
+    val in  = Vec(conf.nEndpoints){new PairedDataIO()(new PhysicalNetworkIO()(meta),new PhysicalNetworkIO()(data))}.flip 
+    val out = Vec(conf.nEndpoints){new PairedDataIO()(new PhysicalNetworkIO()(meta),new PhysicalNetworkIO()(data))}
+  }
+
+  val metaRdyVecs = List.fill(conf.nEndpoints)(Vec(conf.nEndpoints){Bool()})
+  val dataRdyVecs = List.fill(conf.nEndpoints)(Vec(conf.nEndpoints){Bool()})
+  val rdyVecs = metaRdyVecs zip dataRdyVecs
+
+  io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
+    val rrarb = new PairedLockingRRArbiter(conf.nEndpoints, count, needsLock)(io.in(0).meta.bits.clone, io.in(0).data.bits.clone)
+    rrarb.io.in zip io.in zip rdys._1 zip rdys._2 map { case (((arb, in), meta_rdy), data_rdy) => {
+      arb.meta.valid := in.meta.valid && (in.meta.bits.header.dst === UFix(i)) 
+      arb.meta.bits := in.meta.bits
+      meta_rdy := arb.meta.ready && (in.meta.bits.header.dst === UFix(i))
+      arb.data.valid := in.data.valid && (in.data.bits.header.dst === UFix(i)) 
+      arb.data.bits := in.data.bits
+      data_rdy := arb.data.ready && (in.data.bits.header.dst === UFix(i))
+    }}
+    out <> rrarb.io.out
+  }}
+  for(i <- 0 until conf.nEndpoints) {
+    io.in(i).meta.ready := rdyVecs.map(r => r._1(i)).reduceLeft(_||_)
+    io.in(i).data.ready := rdyVecs.map(r => r._2(i)).reduceLeft(_||_)
+  }
+}
+
+case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
+
+class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
+  val src = UFix(width = conf.idBits)
+  val dst = UFix(width = conf.idBits)
+}
+
+class PhysicalNetworkIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
+  val header = (new PhysicalHeader)
+  val payload = data
+  override def clone = { new PhysicalNetworkIO()(data).asInstanceOf[this.type] }
+}
+
+abstract class PhysicalNetwork(conf: PhysicalNetworkConfiguration) extends Component
+
+class BasicCrossbar[T <: Data](count: Int = 1)(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
+  val io = new Bundle {
+    val in  = Vec(conf.nEndpoints){(new FIFOIO){(new PhysicalNetworkIO){data}}}.flip 
+    val out = Vec(conf.nEndpoints){(new FIFOIO){(new PhysicalNetworkIO){data}}}
+  }
+
+  val rdyVecs = List.fill(conf.nEndpoints)(Vec(conf.nEndpoints){Bool()})
+
+  io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
+    val rrarb = (new LockingRRArbiter(conf.nEndpoints, count)){io.in(0).bits.clone}
+    (rrarb.io.in, io.in, rdys).zipped.map{ case (arb, in, rdy) => {
+      arb.valid := in.valid && (in.bits.header.dst === UFix(i)) 
+      arb.bits := in.bits
+      rdy := arb.ready && (in.bits.header.dst === UFix(i))
+    }}
+    out <> rrarb.io.out
+  }}
+  for(i <- 0 until conf.nEndpoints) {
+    io.in(i).ready := rdyVecs.map(r => r(i)).reduceLeft(_||_)
+  }
+}
+
+case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int, nMasters: Int, nClients: Int)
+
+abstract class LogicalNetwork[TileLinkType <: Bundle](endpoints: Seq[CoherenceAgentRole])(implicit conf: LogicalNetworkConfiguration) extends Component {
+  override val io: Vec[TileLinkType]
+  val physicalNetworks: Seq[PhysicalNetwork]
+  require(endpoints.length == conf.nEndpoints)
+}
+
+class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
+  val src = UFix(width = conf.idBits)
+  val dst = UFix(width = conf.idBits)
+}
+
+object FIFOedLogicalNetworkIOWrapper {
+  def apply[T <: Data](in: FIFOIO[T], src: UFix = UFix(0), dst: UFix = UFix(0))(implicit conf: LogicalNetworkConfiguration) = {
+    val shim = (new FIFOedLogicalNetworkIOWrapper(src, dst)){ in.bits.clone }
+    shim.io.in.valid := in.valid
+    shim.io.in.bits := in.bits
+    in.ready := shim.io.in.ready
+    shim.io.out
+  }
+}
+class FIFOedLogicalNetworkIOWrapper[T <: Data](src: UFix, dst: UFix)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component {
+  val io = new Bundle {
+    val in = (new FIFOIO){ data }.flip
+    val out = (new FIFOIO){(new LogicalNetworkIO){ data }} 
+  }
+  io.out.valid := io.in.valid
+  io.out.bits.payload := io.in.bits
+  io.out.bits.header.dst := dst
+  io.out.bits.header.src := src
+  io.in.ready := io.out.ready
+}
+
+object FIFOedLogicalNetworkIOUnwrapper {
+  def apply[T <: Data](in: FIFOIO[LogicalNetworkIO[T]])(implicit conf: LogicalNetworkConfiguration) = {
+    val shim = (new FIFOedLogicalNetworkIOUnwrapper){ in.bits.payload.clone }
+    shim.io.in.valid := in.valid
+    shim.io.in.bits := in.bits
+    in.ready := shim.io.in.ready
+    shim.io.out
+  }
+}
+class FIFOedLogicalNetworkIOUnwrapper[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component {
+  val io = new Bundle {
+    val in = (new FIFOIO){(new LogicalNetworkIO){ data }}.flip
+    val out = (new FIFOIO){ data }
+  }
+  io.out.valid := io.in.valid
+  io.out.bits := io.in.bits.payload
+  io.in.ready := io.out.ready
+}
+
+class LogicalNetworkIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends Bundle {
+  val header = new LogicalHeader
+  val payload = data
+  override def clone = { new LogicalNetworkIO()(data).asInstanceOf[this.type] }
+}
diff --git a/uncore/src/package.scala b/uncore/src/package.scala
index 754621ad..a92f739c 100644
--- a/uncore/src/package.scala
+++ b/uncore/src/package.scala
@@ -1,204 +1,8 @@
-package object uncore {
-import Chisel._
-import Node._
-import scala.collection.mutable.Stack
-
-//TODO: Remove these Networking classes from the package object once Scala bug
-//SI-3439 is resolved.
-
-implicit def toOption[A](a: A) = Option(a)
-
-class PairedDataIO[M <: Data, D <: Data]()(m: => M, d: => D) extends Bundle {
-  val meta = new FIFOIO()(m)
-  val data = new FIFOIO()(d)
-  override def clone = { new PairedDataIO()(m,d).asInstanceOf[this.type] }
-}
-
-class PairedArbiterIO[M <: Data, D <: Data](n: Int)(m: => M, d: => D) extends Bundle {
-  val in  = Vec(n) { new PairedDataIO()(m,d) }.flip
-  val out = new PairedDataIO()(m,d)  
-  val meta_chosen = Bits(OUTPUT, log2Up(n)) 
-  val data_chosen = Bits(OUTPUT, log2Up(n)) 
-  override def clone = { new PairedArbiterIO(n)(m,d).asInstanceOf[this.type] }
-}
-
-class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock: Option[M => Bool] = None)(meta: => M, data: => D) extends Component {
-  require(isPow2(count))
-  val io = new PairedArbiterIO(n)(meta,data)
-  val locked  = if(count > 1) Reg(resetVal = Bool(false)) else Bool(false)
-  val lockIdx = if(count > 1) Reg(resetVal = UFix(n-1)) else UFix(n-1)
-  val grant = List.fill(n)(Bool())
-  val meta_chosen = Bits(width = log2Up(n))
-
-  val chosen_meta_has_data = needsLock.map(_(io.in(meta_chosen).meta.bits)).getOrElse(Bool(true))
-  val valid_meta_has_data = io.in(meta_chosen).meta.valid && chosen_meta_has_data
-  val grant_chosen_meta = !(locked && chosen_meta_has_data)
-  (0 until n).map(i => io.in(i).meta.ready := grant(i) && grant_chosen_meta && io.out.meta.ready)
-  (0 until n).map(i => io.in(i).data.ready := Mux(locked, lockIdx === UFix(i), grant(i) && valid_meta_has_data) && io.out.data.ready)
-  io.out.meta.valid := io.in(meta_chosen).meta.valid && grant_chosen_meta
-  io.out.data.valid := Mux(locked, io.in(lockIdx).data.valid, io.in(meta_chosen).data.valid && valid_meta_has_data)
-  io.out.meta.bits := io.in(meta_chosen).meta.bits
-  io.out.data.bits := Mux(locked, io.in(lockIdx).data.bits, io.in(meta_chosen).data.bits)
-  io.meta_chosen := meta_chosen
-  io.data_chosen := Mux(locked, lockIdx, meta_chosen)
-
-  if(count > 1){
-    val cnt = Reg(resetVal = UFix(0, width = log2Up(count)))
-    val cnt_next = cnt + UFix(1)
-    when(io.out.data.fire()){
-      cnt := cnt_next
-      when(cnt_next === UFix(0)) {
-        locked := Bool(false)
-      }
-    }
-    when(io.out.meta.fire()) {
-      when(needsLock.map(_(io.out.meta.bits)).getOrElse(Bool(true))) {
-        when(!locked) {
-          locked := Bool(true)
-          lockIdx := Vec(io.in.map{in => in.meta.fire()}){Bool()}.indexWhere{i: Bool => i} 
-        }
-      }
-    }
-  }
-  val last_grant = Reg(resetVal = Bits(0, log2Up(n)))
-  val ctrl = ArbiterCtrl((0 until n).map(i => io.in(i).meta.valid && UFix(i) > last_grant) ++ io.in.map(_.meta.valid))
-  (0 until n).map(i => grant(i) := ctrl(i) && UFix(i) > last_grant || ctrl(i + n))
-
-  var choose = Bits(n-1)
-  for (i <- n-2 to 0 by -1)
-    choose = Mux(io.in(i).meta.valid, Bits(i), choose)
-  for (i <- n-1 to 1 by -1)
-    choose = Mux(io.in(i).meta.valid && UFix(i) > last_grant, Bits(i), choose)
-  meta_chosen := choose
-
-  when (io.out.meta.fire()) { last_grant := meta_chosen }
-}
-
-class PairedCrossbar[M <: Data, D <: Data](count: Int, needsLock: Option[BasicCrossbarIO[M] => Bool] = None)(meta: => M, data: => D)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
-  val io = new Bundle {
-    val in  = Vec(conf.nEndpoints){new PairedDataIO()(new BasicCrossbarIO()(meta),new BasicCrossbarIO()(data))}.flip 
-    val out = Vec(conf.nEndpoints){new PairedDataIO()(new BasicCrossbarIO()(meta),new BasicCrossbarIO()(data))}
-  }
-
-  val metaRdyVecs = List.fill(conf.nEndpoints)(Vec(conf.nEndpoints){Bool()})
-  val dataRdyVecs = List.fill(conf.nEndpoints)(Vec(conf.nEndpoints){Bool()})
-  val rdyVecs = metaRdyVecs zip dataRdyVecs
-
-  io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
-    val rrarb = new PairedLockingRRArbiter(conf.nEndpoints, count, needsLock)(io.in(0).meta.bits.clone, io.in(0).data.bits.clone)
-    rrarb.io.in zip io.in zip rdys._1 zip rdys._2 map { case (((arb, in), meta_rdy), data_rdy) => {
-      arb.meta.valid := in.meta.valid && (in.meta.bits.header.dst === UFix(i)) 
-      arb.meta.bits := in.meta.bits
-      meta_rdy := arb.meta.ready && (in.meta.bits.header.dst === UFix(i))
-      arb.data.valid := in.data.valid && (in.data.bits.header.dst === UFix(i)) 
-      arb.data.bits := in.data.bits
-      data_rdy := arb.data.ready && (in.data.bits.header.dst === UFix(i))
-    }}
-    out <> rrarb.io.out
-  }}
-  for(i <- 0 until conf.nEndpoints) {
-    io.in(i).meta.ready := rdyVecs.map(r => r._1(i)).reduceLeft(_||_)
-    io.in(i).data.ready := rdyVecs.map(r => r._2(i)).reduceLeft(_||_)
-  }
-}
-
-case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
-
-class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
-  val src = UFix(width = conf.idBits)
-  val dst = UFix(width = conf.idBits)
-}
-
-abstract class PhysicalNetworkIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
-  val header = (new PhysicalHeader)
-  val payload = data
-}
-
-class BasicCrossbarIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetworkIO()(data)(conf) {
-  override def clone = { new BasicCrossbarIO()(data).asInstanceOf[this.type] }
-}
-
-abstract class PhysicalNetwork(conf: PhysicalNetworkConfiguration) extends Component
-
-class BasicCrossbar[T <: Data](count: Int = 1)(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
-  val io = new Bundle {
-    val in  = Vec(conf.nEndpoints){(new FIFOIO){(new BasicCrossbarIO){data}}}.flip 
-    val out = Vec(conf.nEndpoints){(new FIFOIO){(new BasicCrossbarIO){data}}}
-  }
-
-  val rdyVecs = List.fill(conf.nEndpoints)(Vec(conf.nEndpoints){Bool()})
-
-  io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
-    val rrarb = (new LockingRRArbiter(conf.nEndpoints, count)){io.in(0).bits.clone}
-    (rrarb.io.in, io.in, rdys).zipped.map{ case (arb, in, rdy) => {
-      arb.valid := in.valid && (in.bits.header.dst === UFix(i)) 
-      arb.bits := in.bits
-      rdy := arb.ready && (in.bits.header.dst === UFix(i))
-    }}
-    out <> rrarb.io.out
-  }}
-  for(i <- 0 until conf.nEndpoints) {
-    io.in(i).ready := rdyVecs.map(r => r(i)).reduceLeft(_||_)
-  }
-}
-
-case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int, nMasters: Int, nClients: Int)
-
-abstract class LogicalNetwork[TileLinkType <: Bundle](endpoints: Seq[CoherenceAgentRole])(implicit conf: LogicalNetworkConfiguration) extends Component {
-  override val io: Vec[TileLinkType]
-  val physicalNetworks: Seq[PhysicalNetwork]
-  require(endpoints.length == conf.nEndpoints)
-}
-
-class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
-  val src = UFix(width = conf.idBits)
-  val dst = UFix(width = conf.idBits)
-}
-
-object FIFOedLogicalNetworkIOWrapper {
-  def apply[T <: Data](in: FIFOIO[T], src: UFix = UFix(0), dst: UFix = UFix(0))(implicit conf: LogicalNetworkConfiguration) = {
-    val shim = (new FIFOedLogicalNetworkIOWrapper(src, dst)){ in.bits.clone }
-    shim.io.in.valid := in.valid
-    shim.io.in.bits := in.bits
-    in.ready := shim.io.in.ready
-    shim.io.out
-  }
-}
-class FIFOedLogicalNetworkIOWrapper[T <: Data](src: UFix, dst: UFix)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component {
-  val io = new Bundle {
-    val in = (new FIFOIO){ data }.flip
-    val out = (new FIFOIO){(new LogicalNetworkIO){ data }} 
-  }
-  io.out.valid := io.in.valid
-  io.out.bits.payload := io.in.bits
-  io.out.bits.header.dst := dst
-  io.out.bits.header.src := src
-  io.in.ready := io.out.ready
-}
-
-object FIFOedLogicalNetworkIOUnwrapper {
-  def apply[T <: Data](in: FIFOIO[LogicalNetworkIO[T]])(implicit conf: LogicalNetworkConfiguration) = {
-    val shim = (new FIFOedLogicalNetworkIOUnwrapper){ in.bits.payload.clone }
-    shim.io.in.valid := in.valid
-    shim.io.in.bits := in.bits
-    in.ready := shim.io.in.ready
-    shim.io.out
-  }
-}
-class FIFOedLogicalNetworkIOUnwrapper[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component {
-  val io = new Bundle {
-    val in = (new FIFOIO){(new LogicalNetworkIO){ data }}.flip
-    val out = (new FIFOIO){ data }
-  }
-  io.out.valid := io.in.valid
-  io.out.bits := io.in.bits.payload
-  io.in.ready := io.out.ready
-}
-
-class LogicalNetworkIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends Bundle {
-  val header = new LogicalHeader
-  val payload = data
-  override def clone = { new LogicalNetworkIO()(data).asInstanceOf[this.type] }
-}
-
+package object uncore extends
+  uncore.constants.MemoryOpConstants with
+  uncore.constants.MemoryInterfaceConstants with
+  uncore.constants.CacheConstants with
+  uncore.constants.AddressConstants 
+{
+  implicit def toOption[A](a: A) = Option(a)
 }
diff --git a/uncore/src/slowio.scala b/uncore/src/slowio.scala
index cf00ae6e..b56b1396 100644
--- a/uncore/src/slowio.scala
+++ b/uncore/src/slowio.scala
@@ -1,7 +1,5 @@
 package uncore
-
 import Chisel._
-import Constants._
 
 class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Component
 {
diff --git a/uncore/src/temp.scala b/uncore/src/temp.scala
deleted file mode 100644
index b2d3fdca..00000000
--- a/uncore/src/temp.scala
+++ /dev/null
@@ -1,13 +0,0 @@
-package uncore
-import _root_.uncore.constants._
-
-//TODO: When compiler bug SI-5604 is fixed in 2.10, remove object Constants and 
-//      mixin Constants traits to package object uncore in package.scala and 
-//      remove import Constants._'s from other .scala files
-object Constants extends 
-  MemoryOpConstants with
-  MemoryInterfaceConstants with
-  CacheConstants with
-  AddressConstants
-{
-}
diff --git a/uncore/src/tilelink.scala b/uncore/src/tilelink.scala
index 2e595c34..3621e73b 100644
--- a/uncore/src/tilelink.scala
+++ b/uncore/src/tilelink.scala
@@ -1,7 +1,5 @@
 package uncore
-
 import Chisel._
-import Constants._
 
 trait HasPhysicalAddress extends Bundle {
   val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
diff --git a/uncore/src/uncore.scala b/uncore/src/uncore.scala
index 9d0de31b..5f87f724 100644
--- a/uncore/src/uncore.scala
+++ b/uncore/src/uncore.scala
@@ -1,7 +1,5 @@
 package uncore
-
 import Chisel._
-import Constants._
 
 class TrackerDependency(implicit conf: UncoreConfiguration)  extends Bundle {
   val tracker_id = Bits(width = MASTER_XACT_ID_MAX_BITS)
@@ -109,7 +107,6 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: Uncore
   val release_data_needs_write = Reg(resetVal = Bool(false))
   val mem_cmd_sent = Reg(resetVal = Bool(false))
   val cmd_to_write = co.getUncachedWriteAcquire(xact.addr, UFix(trackerId))
-  val cmd_to_read = co.getUncachedReadAcquire(xact.addr, UFix(trackerId))
 
   io.has_acquire_conflict := Bool(false)
   io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.meta.bits.payload.addr) && (state != s_idle)
@@ -153,6 +150,7 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: Uncore
       when (release_data_needs_write) {
         doOuterReqWrite(io.master.acquire,
                       io.client.release.data,
+                      cmd_to_write,
                       release_data_needs_write,
                       mem_cmd_sent,
                       init_client_id_)
@@ -264,6 +262,7 @@ class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfigura
       when (release_data_needs_write) {
         doOuterReqWrite(io.master.acquire,
                       io.client.release.data, 
+                      cmd_to_write,
                       release_data_needs_write, 
                       r_w_mem_cmd_sent, 
                       release_data_client_id)
@@ -273,17 +272,19 @@ class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfigura
       when (release_data_needs_write) {
         doOuterReqWrite(io.master.acquire,
                       io.client.release.data,
+                      cmd_to_write,
                       release_data_needs_write,
                       r_w_mem_cmd_sent,
                       release_data_client_id)
       } . elsewhen(acquire_data_needs_write) {
         doOuterReqWrite(io.master.acquire,
                       io.client.acquire.data,
+                      cmd_to_write,
                       acquire_data_needs_write,
                       a_w_mem_cmd_sent,
                       init_client_id_)
       } . elsewhen (x_needs_read) {    
-        doOuterReqRead(io.master.acquire, x_needs_read)
+        doOuterReqRead(io.master.acquire, cmd_to_read, x_needs_read)
       } . otherwise { 
         state := Mux(co.needsAckReply(xact.a_type, UFix(0)), s_ack, 
                   Mux(co.requiresAck(io.client.grant.bits.payload), s_busy, s_idle))
@@ -302,14 +303,12 @@ class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfigura
 }
 
 abstract trait OuterRequestGenerator {
-  val cmd_to_write: Acquire
-  val cmd_to_read: Acquire
   val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
   val mem_cnt_next = mem_cnt + UFix(1)
 
-  def doOuterReqWrite[T <: HasMemData](master_acq: PairedDataIO[LogicalNetworkIO[Acquire],LogicalNetworkIO[AcquireData]], client_data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, desired_client_data_src_id: UFix) {
+  def doOuterReqWrite[T <: HasMemData](master_acq: PairedDataIO[LogicalNetworkIO[Acquire],LogicalNetworkIO[AcquireData]], client_data: FIFOIO[LogicalNetworkIO[T]], cmd: Acquire, trigger: Bool, cmd_sent: Bool, desired_client_data_src_id: UFix) {
     val do_write = client_data.valid && (client_data.bits.header.src === desired_client_data_src_id)
-    master_acq.meta.bits.payload := cmd_to_write
+    master_acq.meta.bits.payload := cmd
     master_acq.data.bits.payload := client_data.bits.payload
     when(master_acq.meta.fire()) {
       cmd_sent := Bool(true)
@@ -329,9 +328,9 @@ abstract trait OuterRequestGenerator {
     }
   }
 
-  def doOuterReqRead(master_acq: PairedDataIO[LogicalNetworkIO[Acquire],LogicalNetworkIO[AcquireData]], trigger: Bool) {
+  def doOuterReqRead(master_acq: PairedDataIO[LogicalNetworkIO[Acquire],LogicalNetworkIO[AcquireData]], cmd: Acquire, trigger: Bool) {
     master_acq.meta.valid := Bool(true)
-    master_acq.meta.bits.payload := cmd_to_read
+    master_acq.meta.bits.payload := cmd
     when(master_acq.meta.ready) {
       trigger := Bool(false)
     }