riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

make fpga Makefile work with updated Makefrag

Browse Source
This commit is contained in:
Andrew Waterman 2013-05-02 05:09:45 -07:00
parent cfa86dba4f
commit d825c9d6e9
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/fpga.scala
View File

@ -39,7 +39,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
} }
io.mem.req_cmd <> Queue(conv.io.mem.req_cmd) io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
io.mem.req_data <> Queue(conv.io.mem.req_data, REFILL_CYCLES) io.mem.req_data <> Queue(conv.io.mem.req_data, REFILL_CYCLES)
conv.io.mem.resp <> Queue(io.mem.resp, 16) conv.io.mem.resp <> Queue(io.mem.resp)
} }
class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component