riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into debug_v013_pr

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Megan Wachs
2017-03-29 14:58:04 -07:00
parent f6e72a3ef6 8dfbf4532a
commit d8033b20fc
5 changed files with 21 additions and 11 deletions
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4
src/main/scala/rocketchip/Configs.scala
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@ -24,7 +24,8 @@ class BasePlatformConfig extends Config((site, here, up) => {
// DTS descriptive parameters
case DTSModel => "ucbbar,rocketchip-unknown"
case DTSCompat => Nil
case DTSTimebase => BigInt(0)
case DTSTimebase => BigInt(1000000) // 1 MHz
case RTCPeriod => 1000 // Implies coreplex clock is DTSTimebase * RTCPeriod = 1 GHz
// TileLink connection parameters
case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
case TLFuzzReadyValid => false
@ -41,7 +42,6 @@ class BasePlatformConfig extends Config((site, here, up) => {
case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
})
/** Actual elaboratable target Configs */