riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into debug_v013_pr

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Megan Wachs
2017-03-29 14:58:04 -07:00
parent f6e72a3ef6 8dfbf4532a
commit d8033b20fc
5 changed files with 21 additions and 11 deletions
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5
src/main/scala/rocket/CSR.scala
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@ -497,11 +497,10 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
when (exception) {
val epc = ~(~io.pc | (coreInstBytes-1))
val write_badaddr = cause isOneOf (Causes.breakpoint,
val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault
)
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
when (trapToDebug) {
when (!reg_debug) {