riscv/rocket-chip
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Clean up some zero-width wire cases using UInt.extract

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This commit is contained in:
Andrew Waterman
2016-07-14 21:42:12 -07:00
parent da512d4230
commit d78f1aacd0
5 changed files with 19 additions and 30 deletions
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8
rocket/src/main/scala/util.scala
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@ -14,10 +14,16 @@ object Util {
implicit def booleanToBool(x: Boolean): Bits = Bool(x)
implicit def intSeqToUIntSeq(x: Seq[Int]): Seq[UInt] = x.map(UInt(_))
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit def sextToConv(x: UInt) = new AnyRef {
implicit class UIntToAugmentedUInt(val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt =
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
def extract(hi: Int, lo: Int): UInt = {
if (hi == lo-1) UInt(0)
else x(hi, lo)
}
}
implicit def booleanToIntConv(x: Boolean) = new AnyRef {