tilelink2 Xbar: decouple ready from valid (#338)
This moves the Xbar from using custom code to using the Arbiter. The arbiter has better ready-valid decoupling.
This commit is contained in:
Wesley W. Terpstra
GitHub
parent
d175bb314d
commit
d787bae0d0
@ -14,56 +14,58 @@ object TLArbiter
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valids.scanLeft(Bool(true))(_ && !_).init
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valids.scanLeft(Bool(true))(_ && !_).init
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def apply[T <: Data](policy: Policy)(sink: IrrevocableIO[T], sources: (UInt, IrrevocableIO[T])*) {
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def apply[T <: Data](policy: Policy)(sink: IrrevocableIO[T], sources: (UInt, IrrevocableIO[T])*) {
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require (sources.size >= 1)
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if (sources.isEmpty) {
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sink.valid := Bool(false)
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val pairs = sources.toList
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val beatsIn = pairs.map(_._1)
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val sourcesIn = pairs.map(_._2)
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// The number of beats which remain to be sent
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val beatsLeft = RegInit(UInt(0))
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val idle = beatsLeft === UInt(0)
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// Who wants access to the sink?
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val valids = sourcesIn.map(_.valid)
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// Arbitrate amongst the requests
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val readys = Vec(policy(valids, idle))
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// Which request wins arbitration?
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val winners = Vec((readys zip valids) map { case (r,v) => r&&v })
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// Confirm the policy works properly
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require (readys.size == valids.size)
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// Never two winners
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val prefixOR = winners.scanLeft(Bool(false))(_||_).init
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assert((prefixOR zip winners) map { case (p,w) => !p || !w } reduce {_ && _})
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// If there was any request, there is a winner
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assert (!valids.reduce(_||_) || winners.reduce(_||_))
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// Track remaining beats
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val maskedBeats = (winners zip beatsIn) map { case (w,b) => Mux(w, b, UInt(0)) }
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val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
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val todoBeats = Mux(idle, initBeats, beatsLeft)
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beatsLeft := todoBeats - sink.fire()
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assert (!sink.fire() || todoBeats =/= UInt(0)) // underflow is impoosible
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// The one-hot source granted access in the previous cycle
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val state = RegInit(Vec.fill(sources.size)(Bool(false)))
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val muxState = Mux(idle, winners, state)
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state := muxState
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val ones = Vec.fill(sources.size)(Bool(true))
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val picked = Mux(idle, ones, state)
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sink.valid := Mux1H(picked, valids)
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if (sources.size > 1) {
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val allowed = Mux(idle, readys, state)
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(sourcesIn zip allowed) foreach { case (s, r) =>
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s.ready := sink.ready && r
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}
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} else {
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} else {
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sourcesIn(0).ready := sink.ready
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val pairs = sources.toList
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}
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val beatsIn = pairs.map(_._1)
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val sourcesIn = pairs.map(_._2)
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sink.bits := Mux1H(muxState, sourcesIn.map(_.bits))
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// The number of beats which remain to be sent
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val beatsLeft = RegInit(UInt(0))
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val idle = beatsLeft === UInt(0)
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// Who wants access to the sink?
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val valids = sourcesIn.map(_.valid)
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// Arbitrate amongst the requests
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val readys = Vec(policy(valids, idle))
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// Which request wins arbitration?
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val winners = Vec((readys zip valids) map { case (r,v) => r&&v })
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// Confirm the policy works properly
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require (readys.size == valids.size)
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// Never two winners
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val prefixOR = winners.scanLeft(Bool(false))(_||_).init
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assert((prefixOR zip winners) map { case (p,w) => !p || !w } reduce {_ && _})
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// If there was any request, there is a winner
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assert (!valids.reduce(_||_) || winners.reduce(_||_))
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// Track remaining beats
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val maskedBeats = (winners zip beatsIn) map { case (w,b) => Mux(w, b, UInt(0)) }
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val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
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val todoBeats = Mux(idle, initBeats, beatsLeft)
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beatsLeft := todoBeats - sink.fire()
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assert (!sink.fire() || todoBeats =/= UInt(0)) // underflow is impoosible
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// The one-hot source granted access in the previous cycle
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val state = RegInit(Vec.fill(sources.size)(Bool(false)))
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val muxState = Mux(idle, winners, state)
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state := muxState
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val ones = Vec.fill(sources.size)(Bool(true))
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val picked = Mux(idle, ones, state)
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sink.valid := Mux1H(picked, valids)
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if (sources.size > 1) {
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val allowed = Mux(idle, readys, state)
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(sourcesIn zip allowed) foreach { case (s, r) =>
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s.ready := sink.ready && r
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}
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} else {
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sourcesIn(0).ready := sink.ready
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}
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sink.bits := Mux1H(muxState, sourcesIn.map(_.bits))
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}
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}
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}
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}
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}
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@ -3,17 +3,9 @@
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package uncore.tilelink2
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package uncore.tilelink2
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import Chisel._
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import Chisel._
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import chisel3.util.IrrevocableIO
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object TLXbar
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class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends LazyModule
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{
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def lowestIndex(requests: Vec[Bool], execute: Bool) = {
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// lowest-index first is stateless; ignore execute
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val ors = Vec(requests.scanLeft(Bool(false))(_ || _).init) // prefix-OR
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Vec((ors zip requests) map { case (o, r) => !o && r })
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}
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}
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class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends LazyModule
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{
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{
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def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId))
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def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId))
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def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
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def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
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@ -103,7 +95,6 @@ class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extend
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// Handle size = 1 gracefully (Chisel3 empty range is broken)
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// Handle size = 1 gracefully (Chisel3 empty range is broken)
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def trim(id: UInt, size: Int) = if (size <= 1) UInt(0) else id(log2Ceil(size)-1, 0)
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def trim(id: UInt, size: Int) = if (size <= 1) UInt(0) else id(log2Ceil(size)-1, 0)
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def transpose(x: Seq[Seq[Bool]]) = Vec.tabulate(x(0).size) { i => Vec.tabulate(x.size) { j => x(j)(i) } }
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// Transform input bundle sources (sinks use global namespace on both sides)
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// Transform input bundle sources (sinks use global namespace on both sides)
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val in = Wire(Vec(io.in.size, TLBundle(wide_bundle)))
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val in = Wire(Vec(io.in.size, TLBundle(wide_bundle)))
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@ -129,117 +120,61 @@ class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extend
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io.out(i).e.bits.sink := trim(out(i).e.bits.sink, r.size)
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io.out(i).e.bits.sink := trim(out(i).e.bits.sink, r.size)
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}
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}
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// The crossbar cross-connection state; defined later
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val addressA = (in zip node.edgesIn) map { case (i, e) => e.address(i.a.bits) }
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val grantedAIO = Wire(Vec(in .size, Vec(out.size, Bool())))
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val addressC = (in zip node.edgesIn) map { case (i, e) => e.address(i.c.bits) }
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val grantedBOI = Wire(Vec(out.size, Vec(in .size, Bool())))
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val grantedCIO = Wire(Vec(in .size, Vec(out.size, Bool())))
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val grantedDOI = Wire(Vec(out.size, Vec(in .size, Bool())))
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val grantedEIO = Wire(Vec(in .size, Vec(out.size, Bool())))
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val grantedAOI = transpose(grantedAIO)
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val requestAIO = Vec(addressA.map { i => Vec(outputPorts.map { o => o(i) }) })
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val grantedBIO = transpose(grantedBOI)
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val requestCIO = Vec(addressC.map { i => Vec(outputPorts.map { o => o(i) }) })
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val grantedCOI = transpose(grantedCIO)
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val requestBOI = Vec(out.map { o => Vec(inputIdRanges.map { i => i.contains(o.b.bits.source) }) })
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val grantedDIO = transpose(grantedDOI)
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val requestDOI = Vec(out.map { o => Vec(inputIdRanges.map { i => i.contains(o.d.bits.source) }) })
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val grantedEOI = transpose(grantedEIO)
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val requestEIO = Vec(in.map { i => Vec(outputIdRanges.map { o => o.contains(i.e.bits.sink) }) })
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// Mux1H passes a single-source through unmasked. That's bad for control.
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val beatsAI = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats(i.a.bits) })
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def Mux1C(sel: Seq[Bool], ctl: Seq[Bool]) = (sel zip ctl).map{ case (a,b) => a && b }.reduce(_ || _)
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val beatsBO = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats(o.b.bits) })
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val beatsCI = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats(i.c.bits) })
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// Mux clients to managers
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val beatsDO = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats(o.d.bits) })
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for (o <- 0 until out.size) {
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val beatsEI = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats(i.e.bits) })
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out(o).a.valid := Mux1C(grantedAOI(o), in.map(_.a.valid))
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out(o).a.bits := Mux1H(grantedAOI(o), in.map(_.a.bits))
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out(o).b.ready := Mux1C(grantedBOI(o), in.map(_.b.ready))
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out(o).c.valid := Mux1C(grantedCOI(o), in.map(_.c.valid))
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out(o).c.bits := Mux1H(grantedCOI(o), in.map(_.c.bits))
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out(o).d.ready := Mux1C(grantedDOI(o), in.map(_.d.ready))
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out(o).e.valid := Mux1C(grantedEOI(o), in.map(_.e.valid))
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out(o).e.bits := Mux1H(grantedEOI(o), in.map(_.e.bits))
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}
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// Mux managers to clients
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for (i <- 0 until in.size) {
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in(i).a.ready := Mux1C(grantedAIO(i), out.map(_.a.ready))
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in(i).b.valid := Mux1C(grantedBIO(i), out.map(_.b.valid))
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in(i).b.bits := Mux1H(grantedBIO(i), out.map(_.b.bits))
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in(i).c.ready := Mux1C(grantedCIO(i), out.map(_.c.ready))
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in(i).d.valid := Mux1C(grantedDIO(i), out.map(_.d.valid))
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in(i).d.bits := Mux1H(grantedDIO(i), out.map(_.d.bits))
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in(i).e.ready := Mux1C(grantedEIO(i), out.map(_.e.ready))
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}
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val addressA = (in zip node.edgesIn) map { case (i, e) => (i.a.valid, e.address(i.a.bits)) }
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val addressC = (in zip node.edgesIn) map { case (i, e) => (i.c.valid, e.address(i.c.bits)) }
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val requestAIO = Vec(addressA.map { i => Vec(outputPorts.map { o => i._1 && o(i._2) }) })
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val requestCIO = Vec(addressC.map { i => Vec(outputPorts.map { o => i._1 && o(i._2) }) })
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val requestBOI = Vec(out.map { o => Vec(inputIdRanges.map { i => o.b.valid && i.contains(o.b.bits.source) }) })
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val requestDOI = Vec(out.map { o => Vec(inputIdRanges.map { i => o.d.valid && i.contains(o.d.bits.source) }) })
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val requestEIO = Vec(in.map { i => Vec(outputIdRanges.map { o => i.e.valid && o.contains(i.e.bits.sink) }) })
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val beatsA = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats(i.a.bits) })
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val beatsB = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats(o.b.bits) })
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val beatsC = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats(i.c.bits) })
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val beatsD = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats(o.d.bits) })
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val beatsE = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats(i.e.bits) })
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// Which pairs support support transfers
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// Which pairs support support transfers
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val maskIO = Vec.tabulate(in.size) { i => Vec.tabulate(out.size) { o =>
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def transpose[T](x: Seq[Seq[T]]) = Seq.tabulate(x(0).size) { i => Seq.tabulate(x.size) { j => x(j)(i) } }
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Bool(node.edgesIn(i).client.anySupportProbe && node.edgesOut(o).manager.anySupportAcquire)
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def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
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} }
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val maskOI = transpose(maskIO)
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// Mask out BCE channel connections (to be optimized away) for transfer-incapable pairings
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// Replicate an input port to each output port
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def mask(a: Seq[Seq[Bool]], b: Seq[Seq[Bool]]) =
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def fanout[T <: TLChannel](input: IrrevocableIO[T], select: Seq[Bool]) = {
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Vec((a zip b) map { case (x, y) => Vec((x zip y) map { case (a, b) => a && b }) })
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val filtered = Wire(Vec(select.size, input))
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for (i <- 0 until select.size) {
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grantedAIO := arbitrate( requestAIO, beatsA, out.map(_.a.fire()))
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filtered(i).bits := input.bits
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grantedBOI := mask(arbitrate(mask(requestBOI, maskOI), beatsB, in .map(_.b.fire())), maskOI)
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filtered(i).valid := input.valid && select(i)
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grantedCIO := mask(arbitrate(mask(requestCIO, maskIO), beatsC, out.map(_.c.fire())), maskIO)
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grantedDOI := arbitrate( requestDOI, beatsD, in .map(_.d.fire()))
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grantedEIO := mask(arbitrate(mask(requestEIO, maskIO), beatsE, out.map(_.e.fire())), maskIO)
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def arbitrate(request: Seq[Seq[Bool]], beats: Seq[UInt], progress: Seq[Bool]) = {
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request foreach { row => require (row.size == progress.size) } // consistent # of resources
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request foreach { resources => // only one resource is requested
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val prefixOR = resources.scanLeft(Bool(false))(_ || _).init
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assert (!(prefixOR zip resources).map{case (a, b) => a && b}.reduce(_ || _))
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}
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}
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transpose((transpose(request) zip progress).map { case (r,p) => arbitrate1(r, beats, p) })
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input.ready := Mux1H(select, filtered.map(_.ready))
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filtered
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}
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}
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def arbitrate1(requests: Vec[Bool], beats: Seq[UInt], progress: Bool) = {
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// Fanout the input sources to the output sinks
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require (requests.size == beats.size) // consistent # of requesters
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val portsAOI = transpose((in zip requestAIO) map { case (i, r) => fanout(i.a, r) })
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val portsBIO = transpose((out zip requestBOI) map { case (o, r) => fanout(o.b, r) })
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val portsCOI = transpose((in zip requestCIO) map { case (i, r) => fanout(i.c, r) })
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val portsDIO = transpose((out zip requestDOI) map { case (o, r) => fanout(o.d, r) })
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val portsEOI = transpose((in zip requestEIO) map { case (i, r) => fanout(i.e, r) })
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val beatsLeft = RegInit(UInt(0))
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// Arbitrate amongst the sources
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val idle = beatsLeft === UInt(0)
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for (o <- 0 until out.size) {
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val allowI = Seq.tabulate(in.size) { i =>
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node.edgesIn(i).client.anySupportProbe &&
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node.edgesOut(o).manager.anySupportAcquire
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}
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TLArbiter(policy)(out(o).a, (beatsAI zip portsAOI(o) ):_*)
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TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), allowI):_*)
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TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), allowI):_*)
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}
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// Apply policy to select which requester wins
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for (i <- 0 until in.size) {
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val winners = Vec(policy(requests, idle))
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val allowO = Seq.tabulate(out.size) { o =>
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node.edgesIn(i).client.anySupportProbe &&
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// Winners must be a subset of requests
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node.edgesOut(o).manager.anySupportAcquire
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assert ((winners zip requests).map { case (w,r) => !w || r } .reduce(_ && _))
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}
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// There must be only one winner
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TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), allowO):_*)
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val prefixOR = winners.scanLeft(Bool(false))(_ || _).init
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TLArbiter(policy)(in(i).d, (beatsDO zip portsDIO(i) ):_*)
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assert ((prefixOR zip winners).map { case (p,w) => !p || !w }.reduce(_ && _))
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// Supposing we take the winner as input, how many beats must be sent?
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val maskedBeats = (winners zip beats).map { case (w,b) => Mux(w, b, UInt(0)) }
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val initBeats = maskedBeats.reduceLeft(_ | _) // no winner => 0 beats
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// What is the counter state before progress?
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val todoBeats = Mux(idle, initBeats, beatsLeft)
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// Apply progress and register the result
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beatsLeft := todoBeats - progress.asUInt
|
|
||||||
assert (!progress || todoBeats =/= UInt(0)) // underflow should be impossible
|
|
||||||
|
|
||||||
// The previous arbitration state of the resource
|
|
||||||
val state = RegInit(Vec.fill(requests.size)(Bool(false)))
|
|
||||||
// Only take a new value while idle
|
|
||||||
val muxState = Mux(idle, winners, state)
|
|
||||||
state := muxState
|
|
||||||
|
|
||||||
muxState
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user