From d771f37e7eee1c880f0a4f7ce730e486d868db36 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 18 Aug 2016 10:54:24 -0700 Subject: [PATCH] rename BusPorts to ExternalClients --- coreplex/src/main/scala/Configs.scala | 2 +- coreplex/src/main/scala/Coreplex.scala | 21 +++++++++---------- .../src/main/scala/DirectGroundTest.scala | 2 +- coreplex/src/main/scala/UnitTest.scala | 2 +- src/main/scala/Configs.scala | 2 +- src/main/scala/RocketChip.scala | 10 ++++----- 6 files changed, 19 insertions(+), 20 deletions(-) diff --git a/coreplex/src/main/scala/Configs.scala b/coreplex/src/main/scala/Configs.scala index 4d72d1b1..894cdeb8 100644 --- a/coreplex/src/main/scala/Configs.scala +++ b/coreplex/src/main/scala/Configs.scala @@ -160,7 +160,7 @@ class BaseCoreplexConfig extends Config ( else new MESICoherence(site(L2DirectoryRepresentation))), nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */, nCachingClients = site(NCachedTileLinkPorts), - nCachelessClients = site(NBusPorts) + site(NUncachedTileLinkPorts), + nCachelessClients = site(NExternalClients) + site(NUncachedTileLinkPorts), maxClientXacts = max_int( // L1 cache site(NMSHRs) + 1 /* IOMSHR */, diff --git a/coreplex/src/main/scala/Coreplex.scala b/coreplex/src/main/scala/Coreplex.scala index 8608d700..7ec15395 100644 --- a/coreplex/src/main/scala/Coreplex.scala +++ b/coreplex/src/main/scala/Coreplex.scala @@ -36,8 +36,8 @@ case object RTCPeriod extends Field[Int] case object BootROMFile extends Field[String] /** Export an external MMIO slave port */ case object ExportMMIOPort extends Field[Boolean] -/** Expose additional bus master ports */ -case object NBusPorts extends Field[Int] +/** Expose additional TileLink client ports */ +case object NExternalClients extends Field[Int] /** Extra top-level ports exported from the coreplex */ case object ExtraCoreplexPorts extends Field[Parameters => Bundle] @@ -53,7 +53,7 @@ trait HasCoreplexParameters { lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" }) lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" }) lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" }) - lazy val nBusPorts = p(NBusPorts) + lazy val nExtClients = p(NExternalClients) lazy val exportMMIO = p(ExportMMIOPort) } @@ -68,8 +68,8 @@ class Uncore(implicit val p: Parameters) extends Module val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)) val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip + val ext_uncached = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip val prci = Vec(nTiles, new PRCITileIO).asOutput - val bus = Vec(nBusPorts, new ClientUncachedTileLinkIO()(innerParams)).flip val mmio = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None val interrupts = Vec(p(NExtInterrupts), Bool()).asInput val debug = new DebugBusIO()(p).flip @@ -81,7 +81,7 @@ class Uncore(implicit val p: Parameters) extends Module outmemsys.io.incoherent foreach (_ := false) outmemsys.io.tiles_uncached <> io.tiles_uncached outmemsys.io.tiles_cached <> io.tiles_cached - outmemsys.io.bus <> io.bus + outmemsys.io.ext_uncached <> io.ext_uncached io.mem <> outmemsys.io.mem buildMMIONetwork(p.alterPartial({case TLId => "L2toMMIO"})) @@ -147,7 +147,7 @@ abstract class OuterMemorySystem(implicit val p: Parameters) val io = new Bundle { val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip - val bus = Vec(nBusPorts, new ClientUncachedTileLinkIO()(innerParams)).flip + val ext_uncached = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip val incoherent = Vec(nCachedTilePorts, Bool()).asInput val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)) val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"})) @@ -156,8 +156,7 @@ abstract class OuterMemorySystem(implicit val p: Parameters) /** Use in place of OuterMemorySystem if there are no clients to connect. */ class DummyOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem()(p) { - require(nCachedTilePorts + nUncachedTilePorts == 0) - require(io.bus.isEmpty) + require(nCachedTilePorts + nUncachedTilePorts + nExtClients == 0) io.mem.foreach { tl => tl.acquire.valid := Bool(false) @@ -199,7 +198,7 @@ class DefaultOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem // Wire the tiles to the TileLink client ports of the L1toL2 network, // and coherence manager(s) to the other side l1tol2net.io.clients_cached <> io.tiles_cached - l1tol2net.io.clients_uncached <> io.tiles_uncached ++ io.bus + l1tol2net.io.clients_uncached <> io.tiles_uncached ++ io.ext_uncached l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner // Create a converter between TileLinkIO and MemIO for each channel @@ -232,7 +231,7 @@ abstract class Coreplex(implicit val p: Parameters) extends Module with HasCoreplexParameters { class CoreplexIO(implicit val p: Parameters) extends Bundle { val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)) - val bus = Vec(nBusPorts, new ClientUncachedTileLinkIO()(innerParams)).flip + val ext_clients = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip val mmio = if(p(ExportMMIOPort)) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams)) else None val interrupts = Vec(p(NExtInterrupts), Bool()).asInput val debug = new DebugBusIO()(p).flip @@ -273,7 +272,7 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) { uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten uncore.io.interrupts <> io.interrupts uncore.io.debug <> io.debug - uncore.io.bus <> io.bus + uncore.io.ext_uncached <> io.ext_clients if (exportMMIO) { io.mmio.get <> uncore.io.mmio.get } io.mem <> uncore.io.mem } diff --git a/coreplex/src/main/scala/DirectGroundTest.scala b/coreplex/src/main/scala/DirectGroundTest.scala index 51115e26..5897e124 100644 --- a/coreplex/src/main/scala/DirectGroundTest.scala +++ b/coreplex/src/main/scala/DirectGroundTest.scala @@ -14,7 +14,7 @@ class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topPara io.debug.resp.valid := Bool(false) require(!exportMMIO) - require(nBusPorts == 0) + require(nExtClients == 0) require(nMemChannels == 1) require(nTiles == 1) diff --git a/coreplex/src/main/scala/UnitTest.scala b/coreplex/src/main/scala/UnitTest.scala index 61eba396..8451a8cb 100644 --- a/coreplex/src/main/scala/UnitTest.scala +++ b/coreplex/src/main/scala/UnitTest.scala @@ -8,7 +8,7 @@ import cde.Parameters class UnitTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) { require(!exportMMIO) - require(nBusPorts == 0) + require(nExtClients == 0) require(nMemChannels == 0) io.debug.req.ready := Bool(false) diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 70881caf..f597434f 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -132,7 +132,7 @@ class BasePlatformConfig extends Config ( case ExportMMIOPort => (site(ExtraDevices).size + site(ExtMMIOPorts).size) > 0 case AsyncBusChannels => false case NExtBusAXIChannels => 0 - case NBusPorts => if (site(NExtBusAXIChannels) > 1) 1 else 0 + case NExternalClients => if (site(NExtBusAXIChannels) > 1) 1 else 0 case ConnectExtraPorts => (out: Bundle, in: Bundle, p: Parameters) => out <> in diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index c72a8672..baa8af9a 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -134,7 +134,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters { if (exportMMIO) { periphery.io.mmio_in.get <> coreplex.io.mmio.get } periphery.io.mem_in <> coreplex.io.mem - coreplex.io.bus <> periphery.io.bus_out + coreplex.io.ext_clients <> periphery.io.clients_out coreplex.io.debug <> (if (p(AsyncDebugBus)) @@ -178,7 +178,7 @@ class Periphery(implicit val p: Parameters) extends Module with HasTopLevelParameters { val io = new Bundle { val mem_in = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)).flip - val bus_out = Vec(p(NBusPorts), new ClientUncachedTileLinkIO()(innerParams)) + val clients_out = Vec(p(NExternalClients), new ClientUncachedTileLinkIO()(innerParams)) val mmio_in = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams).flip) else None val mem_axi = Vec(nMemAXIChannels, new NastiIO) val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO) @@ -190,14 +190,14 @@ class Periphery(implicit val p: Parameters) extends Module val extra = p(ExtraTopPorts)(p) } - require(io.bus_out.size <= 1) + require(io.clients_out.size <= 1) - if (io.bus_out.size > 0) { + if (io.clients_out.size > 0) { val conv = Module(new TileLinkIONastiIOConverter) val arb = Module(new NastiArbiter(p(NExtBusAXIChannels))) arb.io.master <> io.bus_axi conv.io.nasti <> conv.io.tl - io.bus_out.head <> conv.io.tl + io.clients_out.head <> conv.io.tl } def connectExternalMMIO(ports: Seq[ClientUncachedTileLinkIO])(implicit p: Parameters) {