riscv/rocket-chip
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DTIM doesn't accept grants

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This commit is contained in:
Andrew Waterman 2017-11-03 15:37:48 -07:00
parent 7bef935d2a
commit d6ede818ee
1 changed files with 9 additions and 1 deletions
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10
src/main/scala/rocket/DCache.scala
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@ -434,7 +434,15 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
// grant // grant
val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d)
val grantIsCached = tl_out.d.bits.opcode.isOneOf(Grant, GrantData) val grantIsCached = {
val res = tl_out.d.bits.opcode.isOneOf(Grant, GrantData)
if (usingDataScratchpad) {
assert(!(tl_out.d.valid && res))
false.B
} else {
res
}
}
val grantIsUncached = tl_out.d.bits.opcode.isOneOf(AccessAck, AccessAckData, HintAck) val grantIsUncached = tl_out.d.bits.opcode.isOneOf(AccessAck, AccessAckData, HintAck)
val grantIsUncachedData = tl_out.d.bits.opcode === AccessAckData val grantIsUncachedData = tl_out.d.bits.opcode === AccessAckData
val grantIsVoluntary = tl_out.d.bits.opcode === ReleaseAck // Clears a different pending bit val grantIsVoluntary = tl_out.d.bits.opcode === ReleaseAck // Clears a different pending bit