From d6e69066a59e20c614ac0c89ba7dac66fb06a9c7 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 1 May 2017 17:41:25 -0700 Subject: [PATCH] Fix ITIM loads (#716) An incorrectly-set ready signal caused bad data to be read from the RAM. --- riscv-tools | 2 +- src/main/scala/rocket/ICache.scala | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/riscv-tools b/riscv-tools index 1bf2c200..25bb7e13 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 1bf2c200443a20291b4f35d565c54eb96dcdf40d +Subproject commit 25bb7e1305d9220dddfbded12c087e8f1372b952 diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 709d3f6c..ef766d93 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -101,7 +101,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val s0_slaveValid = tl_in.map(_.a.fire()).getOrElse(false.B) val s1_slaveValid = RegNext(s0_slaveValid, false.B) val s2_slaveValid = RegNext(s1_slaveValid, false.B) - val s3_slaveValid = RegNext(s2_slaveValid, false.B) + val s3_slaveValid = RegNext(false.B) val s_ready :: s_request :: s_refill :: Nil = Enum(UInt(), 3) val state = Reg(init=s_ready) @@ -226,7 +226,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) io.resp.valid := s2_valid && s2_hit && !s2_disparity tl_in.map { tl => - tl.a.ready := !tl_out.d.fire() && !s1_slaveValid && !s2_slaveValid && !(tl.d.valid && !tl.d.ready) + tl.a.ready := !(tl_out.d.valid || s1_slaveValid || s2_slaveValid || s3_slaveValid) val s1_a = RegEnable(tl.a.bits, s0_slaveValid) when (s0_slaveValid) { val a = tl.a.bits @@ -257,7 +257,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val respValid = RegInit(false.B) respValid := s2_slaveValid || (respValid && !tl.d.ready) when (s2_slaveValid) { - when (edge_in.get.hasData(s1_a)) { s3_slaveValid := true } + when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true } def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i)) s1s3_slaveData := (0 until wordBits/8).map(i => Mux(byteEn(i), s2_data_decoded.corrected, s1s3_slaveData)(8*(i+1)-1, 8*i)).asUInt }