riscv/rocket-chip
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Save a little power during reset by not writing D$ tags (#1287)

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Andrew Waterman 2018-03-15 19:23:09 -05:00 committed by GitHub
parent 78dad3e89b
commit d6bc9c53f0
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1 changed files with 3 additions and 1 deletions
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src/main/scala/rocket/DCache.scala
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@ -700,7 +700,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (s2_correct) { pstore1_storegen_data := s2_data_word_corrected } when (s2_correct) { pstore1_storegen_data := s2_data_word_corrected }
// flushes // flushes
val resetting = Reg(init=Bool(!usingDataScratchpad)) val resetting = RegInit(false.B)
if (!usingDataScratchpad)
when (RegNext(reset)) { resetting := true }
val flushed = Reg(init=Bool(true)) val flushed = Reg(init=Bool(true))
val flushing = Reg(init=Bool(false)) val flushing = Reg(init=Bool(false))
val flushCounter = Reg(init=UInt(nSets * (nWays-1), log2Ceil(nSets * nWays))) val flushCounter = Reg(init=UInt(nSets * (nWays-1), log2Ceil(nSets * nWays)))