riscv/rocket-chip
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Correct the polarity of the non-backup-memory HTIF

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This fails in FIRRTL because <> has polarity now.
This commit is contained in:
Palmer Dabbelt 2016-03-05 21:45:42 -08:00 committed by Palmer Dabbelt
parent 7d5eac189b
commit d697559754
1 changed files with 1 additions and 1 deletions
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src/main/scala/RocketChip.scala
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@ -199,7 +199,7 @@ class Uncore(implicit val p: Parameters) extends Module
VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr, VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW) outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
} else { } else {
htif.io.host.out <> io.host.out io.host.out <> htif.io.host.out
htif.io.host.in <> io.host.in htif.io.host.in <> io.host.in
} }
} }