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Interrupts: Less Pessimistic Synchronization (#714)

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* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
This commit is contained in:
Megan Wachs
2017-04-28 14:49:24 -07:00
committed by GitHub
parent 9b688ce7e2
commit d67738204f
5 changed files with 123 additions and 41 deletions
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11
src/main/scala/tile/Interrupts.scala
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@ -46,12 +46,15 @@ trait HasExternalInterruptsModule {
// go from flat diplomatic Interrupts to bundled TileInterrupts
def decodeCoreInterrupts(core: TileInterrupts) {
val core_ips = Seq(
core.debug,
val async_ips = Seq(core.debug)
val periph_ips = Seq(
core.msip,
core.mtip,
core.meip,
core.seip.getOrElse(Wire(Bool()))) ++ core.lip
core_ips.zip(io.interrupts(0)).foreach { case(c, i) => c := i }
core.seip.getOrElse(Wire(Bool())))
val core_ips = core.lip
(async_ips ++ periph_ips ++ core_ips).zip(io.interrupts(0)).foreach { case(c, i) => c := i }
}
}