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Interrupts: Less Pessimistic Synchronization (#714)

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* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
This commit is contained in:
Megan Wachs
2017-04-28 14:49:24 -07:00
committed by GitHub
parent 9b688ce7e2
commit d67738204f
5 changed files with 123 additions and 41 deletions
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2
src/main/scala/rocketchip/ExampleTop.scala
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@ -9,7 +9,7 @@ import rocketchip._
/** Example Top with Periphery (w/o coreplex) */
abstract class ExampleTop(implicit p: Parameters) extends BaseTop
with PeripheryExtInterrupts
with PeripheryAsyncExtInterrupts
with PeripheryMasterAXI4Mem
with PeripheryMasterAXI4MMIO
with PeripherySlaveAXI4 {